Symbolic analog-circuit analysis has many applications, and is especially useful for analog synthesis and testability analysis. Existing approaches rely on two forms of symbolic expression representation: expanded sum-of-product form or arbitrarily nested form. Expanded form suffers the problem that the number of product terms grows exponentially with the size of a circuit, and approximation has to be used. Nested form is not canonical, i.e., many representations exist for a symbolic expression, and manipulations with the nested form are often complicated. In this paper, we present a new approach to exact and canonical symbolic analysis by exploiting the sparsity and sharing of product terms. It consists of representing the symbolic determinant of a circuit matrix by a graph---called determinant decision diagram (DDD)---and performing symbolic analysis by graph manipulations. We showed that DDD construction, as well as many symbolic analysis algorithms, can be performed in time complex...

A novel hierarchical approach is proposed to symbolic analysis of large analog circuits. The key idea is to use a graph-based representation -- called Determinant Decision Diagram (DDD) -- to represent the symbolic determinant and cofactors associated with the MNA matrix for each subcircuit block. By exploiting the inherent sharing and sparsity of symbolic expressions, DDD is capable of representing a huge number of symbolic product terms in a canonical and highly-compact manner. Further, it enables cofactoring and sensitivity computation to be performed with time linear in the size of DDD. Experimental results have demonstrated that our method outperforms the best-known existing hierarchical symbolic analyzer SCAPP, and sometimes even numerical simulator SPICE.

Symbolic analog-circuit analysis has many applications, and is especially useful for analog synthesis and testability analysis. In this paper, we present a new approach to exact and canonical symbolic analysis by exploiting the sparsity and sharing of product terms. It consists of representing the symbolic determinant of a circuit matrix by a graph---called determinant decision diagram (DDD)---and performing symbolic analysis by graph manipulations. We showed that DDD construction and DDD-based symbolic analysis can be performed in time complexity proportional to the number of DDD vertices. We described a vertex ordering heuristic, and showed that the number of DDD vertices can be quite small---usually orders-of-magnitude less than the number of product terms. The algorithm has been implemented. An order-of-magnitude improvement in both CPU time and memory usages over existing symbolic analyzers ISAAC and Maple-V has been observed for large analog circuits. 1. Introduction Symbolic a...

A new approach is proposed to hierarchical symbolic analysis of large analog integrated circuits. It consists of performing symbolic suppression of each subcircuit to its terminals in terms of subcircuit matrix determinants and cofactors, and applying Cramer's rule to solve symbolically the set of equations at the top level of the circuit hierarchy. The novelty of the proposed approach is to use an annotated, directed and acyclic graph, called Determinant Decision Diagram (DDD), to represent symbolic determinants of subcircuit matrices and cofactors used in subcircuit suppression, as well as symbolic determinants of the top-level circuit matrix and cofactors required in applying Cramer's rule. DDD enables systematically exploiting the inherent sparsity of circuit matrices and the sharing of symbolic expressions. It is capable of representing a huge number of symbolic product terms in a canonical and highly compact manner. The proposed approach is illustrated using a Cauer parameter low...

Abstract—This paper proposes a novel approach to the exact symbolic analysis of very large analog circuits. The new method is based on determinant decision diagrams (DDDs) representing symbolic product terms. But instead of constructing DDD graphs directly from a flat circuit matrix, the new method constructs DDD graphs in a hierarchical way based on hierarchically defined circuit structures. The resulting algorithm can analyze much larger analog circuits exactly than before. The authors show that exact symbolic expressions of a circuit are cancellation-free expressions when the circuit is analyzed hierarchically. With this, the authors propose a novel symbolic decancellation process, which essentially leads to the hierarchical DDD graph constructions. The new algorithm partially avoids the exponential DDD construction time by employing more efficient DDD graph operations during the hierarchical construction. The experimental results show that very large analog circuits, which cannot be analyzed exactly before like UPS and other unstructured circuits up to 100 nodes, can be analyzed by the new approach for the first time. The new approach significantly improves the exact symbolic capacity and promises huge potentials for the applications of exact symbolic analysis. Index Terms—Behavioral modeling, circuit simulation, symbolic analysis. I.

This paper reviews the main last generation symbolic analyzers, comparing them in terms of functionality, pointing out also their shortcomings. The state-of-the-art in this field is also studied, pointing out directions for future research. 1. INTRODUCTION Circuit analysis is a basic milestone for efficient design of integrated circuits. Ever since powerful computers have been available, designers have developed programs to analyze circuits automatically. Today, all electrical engineering professionals and students use electrical simulators (such as HSPICE or ELDO). However, electrical simulators do not cover all the analysis tasks required for integrated circuit design. Essentially, they only serve to verify the performance of previously sized circuits. Among other things, designers must be able to predict the behavior of unsized circuits by tracing relationships among performance figures and design parameters. These relationships may be in the form of transfer functions, poles and ...

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