Abstract—In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this paper, we quantify the difference between the statistical and deterministic optima of leakage power while making no assumptions about the delay model. We develop a framework for deriving a theoretical upper bound on the suboptimality that is incurred by using the deterministic optimum as an approximation for the statistical optimum. We show that for the mean power measure, the deterministic optima is an excellent approximation, and for the mean plus standard deviation measures, the optimality gap increases as the amount of inter-die variation grows, for a suite of benchmark circuits in a 45 nm technology. For large variations, we show that there are excellent linear approximations that can be used to approximate the effects of variation. Therefore, the need to develop special statistical power optimization algorithms is questionable. Index Terms—Algorithms, gate sizing, optimization, physical design, statistical power. I.

Abstract – While technology scaling has presented many new and exciting opportunities, new design challenges have arisen due to increased density, and delay and power variations. Highlevel synthesis has been touted as a solution to these problems, as it can significantly reduce the number of man hours required for a design by raising the level of abstraction. In this paper, we propose a new variation-aware high-level synthesis binding/module selection algorithm, named FastYield, which takes into consideration multiplexers, functional units, registers, and interconnects. Additionally, FastYield connects with the lower levels of the design hierarchy through its inclusion of a timing driven floorplanner guided by a statistical static timing analysis (SSTA) engine which is used to modify/enhance the synthesis solution. FastYield is able to incorporate spatial correlations of process variations in its optimization, which are shown to affect performance yield. On average, FastYield achieves a clock period that is 14.5 % smaller, and a performance yield gain of 78.9%, when compared to a variation-unaware algorithm. By making use of accurate timing information, FastYield’s rebinding improves performance yield by an average of 9.8 % over the initial binding, for the same clock period. To the best of our knowledge, this is the first high-level synthesis binding/module selection algorithm that is layout-driven and variation aware. I.

While technology scaling has presented many new and exciting opportunities, new design challenges have arisen. Smaller feature sizes have led to increased density and large variations in the delay and power characteristics of on-chip devices. Additionally, with the increasing desirability of low-power chips, decreasing power consumption has become a significant priority. Major sources of dynamic power consumption in modern chips include glitches (i.e., spurious signal transitions), the reduction of which are challenges to circuit designers. High-level synthesis has been touted as a solution to these problems, as it can both significantly reduce the number of man hours required for a circuit design, and offer greater opportunities for optimization of design goals, by raising the level of abstraction. In this thesis, we present two resource binding and allocation algorithms that take advantage of the optimization opportunities available at the higher level of abstraction. The first is a new variation-aware high-level synthesis binding and module selection algorithm, named FastYield, which takes into consideration multiplexers,

Abstract- Advanced process technologies impose more significant challenges especially when manufactured circuits exhibit substantial process variations. Consideration of process variations becomes critical to ensure high parametric timing yield. During the design stage, fast estimation of the achievable buffered delay can navigate more accurate and efficient wire planning and timing analysis in floorplanning or global routing. In this paper, we derive approximated first-order canonical forms for buffered delay estimation which considers the effect of process variations and the presence of buffer blockages. We empirically show that an existing deterministic delay estimation method will be over-pessimistic and thus result in unnecessary design rollback. The experimental results also show that our method can estimate buffered delay with 4 % average error but achieve up to 149 times speedup when compared to a state-of-the-art statistical buffer insertion method. I.