Results 1  10
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23
Criticality computation in parameterized statistical timing
 in Proc. Design Automation Conf
, 2006
"... Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult since different paths are frequencylimiting in different parts of the multidimensional process space. Therefore, it is ..."
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Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult since different paths are frequencylimiting in different parts of the multidimensional process space. Therefore, it is desirable to have a new diagnostic metric for robust circuit optimization. This paper presents a novel algorithm to compute the criticality probability of every edge in the timing graph of a design with linear complexity in the circuit size. Using industrial benchmarks, we verify the correctness of our criticality computation via Monte Carlo simulation. We also show that for large industrial designs with 442,000 gates, our algorithm computes all edge criticalities in less than 160 seconds.
Variability Driven Gate Sizing for Binning Yield Optimization
 IN PROCEEDINGS OF ACM/IEEE DESIGN AUTOMATION CONFERENCE
, 2006
"... Process variations result in a considerable spread in the frequency of the fabricated chips. In high performance applications, those chips that fail to meet the nominal frequency after fabrication are either discarded or sold at a loss which is typically proportional to the degree of timing violatio ..."
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Cited by 15 (0 self)
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Process variations result in a considerable spread in the frequency of the fabricated chips. In high performance applications, those chips that fail to meet the nominal frequency after fabrication are either discarded or sold at a loss which is typically proportional to the degree of timing violation. The latter is called binning. In this paper we present a gate sizingbased algorithm that optimally minimizes the binning yieldloss. We make the following contributions: 1) prove the binning yield function to be convex, 2) do not make any assumptions about the sources of variability, and their distribution model, 3) we integrate our strategy with statistical timing analysis tools (STA), without making any assumptions about how STA is done, 4) if the objective is to optimize the traditional yield (and not binning yield) our approach can still optimize the same to a very large extent. Comparison of our approach with sensitivitybased approaches under fabrication variability shows an improvement of on average 72 % in the binning yieldloss with an area overhead of an average 6%, while achieving a 2.69 times speedup under a stringent timing constraint. Moreover we show that a worstcase deterministic approach fails to generate a solution for certain delay constraints. We also show that optimizing the binning yieldloss minimizes the traditional yieldloss with a 61 % improvement from a sensitivitybased approach.
Variationaware task allocation and scheduling for mpsoc
 in IEEE ICCAD
, 2007
"... Abstract — As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable [1]. In this paper ..."
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Abstract — As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable [1]. In this paper, we propose a variationaware task allocation and scheduling algorithm for Multiprocessor SystemonChip (MPSoC) architectures to mitigate the impact of parameter variations. A new design metric, called performance yield and defined as the probability of the assigned schedule meeting the predefined performance constraints, is used to guide the task allocation and scheduling procedure. An efficient yield computation method for task scheduling complements and significantly improves the effectiveness of the proposed variationaware scheduling algorithm. Experimental results show that our variationaware scheduler achieves significant yield improvements. On average, 45 % and 34 % yield improvements over worstcase and nominalcase deterministic schedulers, respectively, can be obtained across the benchmarks by using the proposed variationaware scheduler. I.
VariationAware Routing for FPGAs
 International Sympossium on FieldProgrammable Gate Arrays
, 2007
"... Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the effects of variations. The FPGA community on the other hand, has only recently started focussing on the effects of variati ..."
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Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the effects of variations. The FPGA community on the other hand, has only recently started focussing on the effects of variations. This paper presents a comparative study of the impact of variations on designs mapped to FPGAs and ASICs to get a measure of the severity of the problem in both the FPGA and ASIC domains. We also propose a variation aware router that reduces the yield loss by 7.61X, or the circuit delay by 3.95 % for the same yield for the MCNC benchmarks. 1.
On the Futility of Statistical Power Optimization
"... In response to the increasing variations in integratedcircuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this paper we try to quantify the difference between the statistical and deterministic optima of leakage power while making n ..."
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In response to the increasing variations in integratedcircuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this paper we try to quantify the difference between the statistical and deterministic optima of leakage power while making no assumptions about the delay model. We develop a framework for deriving a theoretical upperbound on the suboptimality that is incurred by using the deterministic optimum as an approximation for the statistical optimum. On average, the bound is 2.4 % for a suite of benchmark circuits in a 45nm technology. We further give an intuitive explanation and show, by using solution rank orders, that the practical suboptimality gap is much lower. Therefore, the need for statistical power modeling for the purpose of optimization is questionable.
A Geometric Programmingbased WorstCase Gate Sizing Method Incorporating Spatial Correlation
"... Abstract — We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worstcase design scheme, but it reduces the pessimism involved in traditional worstcasing methods by incorporating the effect of spatial correlations in the optimization pr ..."
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Abstract — We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worstcase design scheme, but it reduces the pessimism involved in traditional worstcasing methods by incorporating the effect of spatial correlations in the optimization procedure. The pessimism reduction is achieved by employing a bounded model for the parameter variations, in the form of an uncertainty ellipsoid, which captures the spatial correlation information between the physical parameters. The use of the uncertainty ellipsoid, along with the assumption that the random variables, corresponding to the varying parameters, follow a multivariate Gaussian distribution, enables us to size the circuits for a specified timing yield. Using a posynomial delay model, the delay constraints are modified to incorporate uncertainty in the transistor widths and effective channel lengths due to the
Clustering Based Pruning for Statistical Criticality Computation under Process Variations
"... Abstract — We present a new linear time technique to compute criticality information in a timing graph by dividing it into “zones”. Errors in using tightness probabilities for criticality computation are dealt with using a new clustering based pruning algorithm which greatly reduces the size of circ ..."
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Abstract — We present a new linear time technique to compute criticality information in a timing graph by dividing it into “zones”. Errors in using tightness probabilities for criticality computation are dealt with using a new clustering based pruning algorithm which greatly reduces the size of circuitlevel cutsets. Our clustering algorithm gives a 150X speedup compared to a pairwise pruning strategy in addition to ordering edges in a cutset to reduce errors due to Clark’s MAX formulation. The clustering based pruning strategy coupled with a localized sampling technique reduces errors to within 5 % of Monte Carlo simulations with large speedups in runtime. I. INTRODUCTION AND PREVIOUS WORK With scaling of technology, process parameter variations render the circuit delay as unpredictable [6], making signoff ineffective in assuring against chip failure. Recent works concerning Statistical Static Timing Analysis (SSTA) in [1], [9] deal with this issue by treating the delay of gates and
Fast and Accurate Statistical Criticality Computation under Process Variations
"... Abstract — With ever shrinking device geometries, process variations play an increased role in determining the delay of a digital circuit. Under such variations, a gate may lie on the critical path of a manufactured die with a certain probability, called the criticality probability. In this paper, w ..."
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Abstract — With ever shrinking device geometries, process variations play an increased role in determining the delay of a digital circuit. Under such variations, a gate may lie on the critical path of a manufactured die with a certain probability, called the criticality probability. In this paper, we present a new technique to compute the statistical criticality information in a digital circuit under process variations by linearly traversing the edges in its timing graph and dividing it into “zones”. We investigate the sources of error in using tightness probabilities for criticality computation with Clark’s statistical maximum formulation. The errors are dealt with using a new clustering based pruning algorithm which greatly reduces the size of circuitlevel cutsets improving both accuracy and runtime over the current state of the art. On large benchmark circuits, our clustering algorithm gives about a 250X speedup compared to a pairwise pruning
Profit Aware Circuit Design Under Process Variations Considering
"... Abstract—In this paper, a profitaware design metric is proposed to consider the overall merit of a design in terms of power and performance. A statistical design methodology is then developed to improve the economic merit of a design considering frequency binning and product price profile. A lowc ..."
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Abstract—In this paper, a profitaware design metric is proposed to consider the overall merit of a design in terms of power and performance. A statistical design methodology is then developed to improve the economic merit of a design considering frequency binning and product price profile. A lowcomplexity sensitivitybased gate sizing algorithm is developed to improve economic gain of a design over its initial yieldoptimized design. Finally, we present an integrated design methodology for simultaneous sizing and bin boundary determination to enhance profit under an area constraint. Experiments on a set of ISCAS’85 benchmarks show in average 19 % improvement in profit for simultaneous sizing and bin boundary determination, considering both leakage power dissipation and delay bounds compared to a design initially optimized for 90 % yield at isoarea in 70nm bulk CMOS technology. Index Terms—Design for profit, frequencybinning, gatelevel sizing, leakage power, statistical delay variation. I.