technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8- m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65 phase margin, and 1.5-V / s average slew rate, while only dissipating 400- W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption. Index Terms—Active feedback, active-capacitive-feedback network, amplifiers, frequency compensation, multistage amplifiers.

Abstract—A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6- m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V / s average slew rate while only dissipating 330 W at 1.5 V, when driving a 25-k //120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies. Index Terms—Amplifiers, dual loop, dual path, frequency compensation, multistage amplifiers. I.

Abstract—This paper presents a low-power stability strategy to significantly reduce the power consumption of a three-stage amplifier using active-feedback frequency compensation (AFFC). The bandwidth of the amplifier can also be enhanced. Simulation results verify that the power dissipation of the AFFC amplifier is reduced by 43 % and the bandwidth is improved by 32.5 % by using the proposed stability strategy. In addition, a dynamic feedforward stage (DFS), which can be embedded into the AFFC amplifier to improve the transient responses without consuming extra power, is proposed. Implemented in a 0.6- m CMOS process, experimental results show that both AFFC amplifiers with and without DFS achieve almost the same small-signal performances while the amplifier with DFS improves both the negative slew rate and negative 1 % settling time by two times. Index Terms—Active feedback, amplifiers, dynamic feedforward stage (DFS), frequency compensation, low-power stability strategy, multistage amplifiers. I.

model. Nested G m -C Compensation (NGCC) N th -Order Analog & Mixed-Signal Center (AMSC) i V 0 V 1 m G 2 m G 1 mf G 1 m C i V out V dd V ss V 1 m g 1 b V 2 b V 2 m g 12 M 22 M 21 M 1 Mf 1 mf g 13 M 14 M 11 M (a) Representation (b) Transistor Level How to Implement a Positive G m ? M22. to parallel in r transisto PMOS a add and M21 Remove , G G If current. additional provide to M21 add then , current Mf1 current M22 , G G If 1 Mf G g g , 22 M 21 M G g g , 14 M 11 M G 1 mf m2 1 mf m2 1 mf 2 m mM22 2 m 1 m mM11 1 m > . > > . = - = - Analog & Mixed-Signal Center (AMSC) dd V ss V 1 m g 2 m g 3 m g 3 M 5 M 4 M - V + V 1 m C 2 m C 3 m C out V 4 m g 2 mf g 3 mf g 3 b V 2 b V 1 b V 1 mf g Four stage operational amplifier with NGCC topology Design Example of a Four-Stage Amplifier Analog & Mixed-Signal Center (AMSC) Measured Performance of the 4-Stage NGCC Op Amp. 2 2 o o 0.22mm 0.22mm Area //20pF 10k 20 // 10k Condition Load 1....

• Design Considerations • Existing approaches • Proposed Approach (1)

• Good voltage gain can be obtained using cascode stages. But these stages are not amenable for LV power supply. • Under LV conditions, large voltage gain can be obtained using cascade amplifiers. That is growing horizontally, rather than vertically. • Direct Cascade of simple (inverting) stages could give the required voltage gain without any control of poles and zeroes. Potential stability problems. • Dynamic behavior for optimal performance requires feedback (and feedforward) circuits. This can solve the stability problems.

Abstract—A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 m CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10 4 clock cycles. Index Terms—ADC, analog-to-digital conversion, background, calibration, capacitor mismatch, CMOS, DAC, dual-ADC, missing codes, pipeline, rapid, split-ADC.