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Activefeedback frequencycompensation technique for lowpower multistage amplifiers
 IEEE J. SolidState Circuits
, 2003
"... technique for lowpower operational amplifiers is presented in this paper. With an activefeedback mechanism, a highspeed block separates the lowfrequency highgain path and highfrequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The ..."
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Cited by 7 (3 self)
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technique for lowpower operational amplifiers is presented in this paper. With an activefeedback mechanism, a highspeed block separates the lowfrequency highgain path and highfrequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the activefeedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a lefthalfplane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Threestage amplifiers based on AFFC and nestedMiller compensation (NMC) techniques have been implemented by a commercial 0.8 m CMOS process. When driving a 120pF capacitive load, the AFFC amplifier achieves over 100dB dc gain, 4.5MHz gainbandwidth product (GBW) , 65 phase margin, and 1.5V / s average slew rate, while only dissipating 400 W power at a 2V supply. Compared to a threestage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption. Index Terms—Active feedback, activecapacitivefeedback network, amplifiers, frequency compensation, multistage amplifiers.
A dualpath bandwidth extension amplifier topology with dualloop parallel compensation
 IEEE J. SolidState Circuits
, 2003
"... Abstract—A dualpath amplifier topology with dualloop parallel compensation technique is proposed for lowpower threestage amplifiers. By using two parallel highspeed paths for highfrequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both ..."
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Cited by 2 (1 self)
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Abstract—A dualpath amplifier topology with dualloop parallel compensation technique is proposed for lowpower threestage amplifiers. By using two parallel highspeed paths for highfrequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6 m CMOS process, the proposed threestage amplifier has over 100dB gain, 7MHz gainbandwidth product, and 3.3V / s average slew rate while only dissipating 330 W at 1.5 V, when driving a 25k //120pF load. The proposed amplifier achieves at least two times improvement in bandwidthtopower and slewratetopower efficiencies than all other reported multistage amplifiers using different compensation topologies. Index Terms—Amplifiers, dual loop, dual path, frequency compensation, multistage amplifiers. I.
Advances in activefeedback frequency compensation with power optimization and transient improvement
 IEEE Transactions on Circuits and Systems
, 2004
"... Abstract—This paper presents a lowpower stability strategy to significantly reduce the power consumption of a threestage amplifier using activefeedback frequency compensation (AFFC). The bandwidth of the amplifier can also be enhanced. Simulation results verify that the power dissipation of the A ..."
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Cited by 2 (1 self)
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Abstract—This paper presents a lowpower stability strategy to significantly reduce the power consumption of a threestage amplifier using activefeedback frequency compensation (AFFC). The bandwidth of the amplifier can also be enhanced. Simulation results verify that the power dissipation of the AFFC amplifier is reduced by 43 % and the bandwidth is improved by 32.5 % by using the proposed stability strategy. In addition, a dynamic feedforward stage (DFS), which can be embedded into the AFFC amplifier to improve the transient responses without consuming extra power, is proposed. Implemented in a 0.6 m CMOS process, experimental results show that both AFFC amplifiers with and without DFS achieve almost the same smallsignal performances while the amplifier with DFS improves both the negative slew rate and negative 1 % settling time by two times. Index Terms—Active feedback, amplifiers, dynamic feedforward stage (DFS), frequency compensation, lowpower stability strategy, multistage amplifiers. I.
An 11Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage
"... Abstract—A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11bit pipelined ADC is presented. Using a dualADC based approach the digital background scheme is validated with a proofofconcept prototype fabricated in a 1.8 V 0.18 m CMOS process, where the ..."
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Abstract—A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11bit pipelined ADC is presented. Using a dualADC based approach the digital background scheme is validated with a proofofconcept prototype fabricated in a 1.8 V 0.18 m CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10 4 clock cycles. Index Terms—ADC, analogtodigital conversion, background, calibration, capacitor mismatch, CMOS, DAC, dualADC, missing codes, pipeline, rapid, splitADC.
A Tutorial
"... model. Nested G m C Compensation (NGCC) N th Order Analog & MixedSignal Center (AMSC) i V 0 V 1 m G 2 m G 1 mf G 1 m C i V out V dd V ss V 1 m g 1 b V 2 b V 2 m g 12 M 22 M 21 M 1 Mf 1 mf g 13 M 14 M 11 M (a) Representation (b) Transistor Level How to Implement a Po ..."
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model. Nested G m C Compensation (NGCC) N th Order Analog & MixedSignal Center (AMSC) i V 0 V 1 m G 2 m G 1 mf G 1 m C i V out V dd V ss V 1 m g 1 b V 2 b V 2 m g 12 M 22 M 21 M 1 Mf 1 mf g 13 M 14 M 11 M (a) Representation (b) Transistor Level How to Implement a Positive G m ? M22. to parallel in r transisto PMOS a add and M21 Remove , G G If current. additional provide to M21 add then , current Mf1 current M22 , G G If 1 Mf G g g , 22 M 21 M G g g , 14 M 11 M G 1 mf m2 1 mf m2 1 mf 2 m mM22 2 m 1 m mM11 1 m > . > > . =  =  Analog & MixedSignal Center (AMSC) dd V ss V 1 m g 2 m g 3 m g 3 M 5 M 4 M  V + V 1 m C 2 m C 3 m C out V 4 m g 2 mf g 3 mf g 3 b V 2 b V 1 b V 1 mf g Four stage operational amplifier with NGCC topology Design Example of a FourStage Amplifier Analog & MixedSignal Center (AMSC) Measured Performance of the 4Stage NGCC Op Amp. 2 2 o o 0.22mm 0.22mm Area //20pF 10k 20 // 10k Condition Load 1....
Low Power Multistage Amplifiers For Large Capacitive Loads By
"... • Design Considerations • Existing approaches • Proposed Approach (1) ..."
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"... • Good voltage gain can be obtained using cascode stages. But these stages are not amenable for LV power supply. • Under LV conditions, large voltage gain can be obtained using cascade amplifiers. That is growing horizontally, rather than vertically. • Direct Cascade of simple (inverting) stages cou ..."
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• Good voltage gain can be obtained using cascode stages. But these stages are not amenable for LV power supply. • Under LV conditions, large voltage gain can be obtained using cascade amplifiers. That is growing horizontally, rather than vertically. • Direct Cascade of simple (inverting) stages could give the required voltage gain without any control of poles and zeroes. Potential stability problems. • Dynamic behavior for optimal performance requires feedback (and feedforward) circuits. This can solve the stability problems.