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The stochastic I-pot: A circuit block for programming bias currents
- IEEE Trans. Circuits Syst. II, Brief Papers
, 2007
"... Abstract—In this brief, we present the “Stochastic I-Pot. ” It is a circuit element that allows for digitally programming a precise bias current ranging over many decades, from pico-amperes up to hundreds of micro-amperes. I-Pot blocks can be chained within a chip to allow for any arbitrary number o ..."
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Abstract—In this brief, we present the “Stochastic I-Pot. ” It is a circuit element that allows for digitally programming a precise bias current ranging over many decades, from pico-amperes up to hundreds of micro-amperes. I-Pot blocks can be chained within a chip to allow for any arbitrary number of programmable bias currents. The approach only requires to provide the chip with three external pins, the use of an external current measuring instrument, and a computer. This way, once all internal I-Pots have been characterized, they can be programmed through a computer to provide any desired current bias value with very low error. The circuit block turns out to be very practical for experimenting with new circuits (specially when a large number of biases are required), testing wide ranges of biases, introducing means for current mismatch calibration, offsets compensations, etc. using a reduced number of chip pins. We show experimental results of generating bias currents with errors of 0.38 % (8 bits) for currents varying from 176 A to 19.6 pA. Temperature effects are characterized. Index Terms—Analog circuits, current-mode circuits, current biases, low-power circuits, mismatch, programmable current sources, reference currents. I.
A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter
"... A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6-m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without lowthreshold devices by using a bootstrapping technique that does not subj ..."
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A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6-m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without lowthreshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 0.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW. Index Terms---Analog to digital, low voltage, reliability. I. INTRODUCTION I N mixed-mode analog-to-digital (A/D) interfaces, there are many applications where a video-rate A/D converter (ADC) is integrated with complex digital signal-processing (DSP) blocks in a compatible, low-cost technology---particularly CMOS. Such applications include camcorders, wireless localarea -network transceivers, and digital set-top boxes. Ad...

