Abstract—A low-voltage opamp-reset switching technique (ORST) that does not use clock boosting, bootstrapping, switched-opamp (SO), or threshold voltage scaling is presented. This technique greatly reduces device reliability issues. Unlike the SO technique, the opamps stay active for all clock phases and, therefore, the ORST is suitable for high-speed applications. This new switching technique is applied to the design of a 10-bit 25–MS/s pipelined analog-to-digital converter (ADC). The prototype ADC was fabricated in a 0.35- m CMOS process and demonstrates 55-dB signal-to-noise ratio, 55-dB spurious-free dynamic range, and 48–dB signal-to-noise-plus-distortion ratio performance with a 1.4-V power supply. The total power consumption is 21 mW. The ADC’s minimum operating power supply is 1.3 V @ „r € aHW VA and the maximum operating frequency is 32 MS/s. The ORST is fully compatible with future low-voltage submicron CMOS processes. Index Terms—Analog-to-digital converter (ADC), low voltage, opamp-reset switching technique (ORST), pipeline. I.

Abstract—An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77-dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR,

Abstract—The problem of low-voltage operation of switched-capacitor circuits is discussed, and several solutions based on using unity-gain-reset of the opamps are proposed. Due to the feedback structure, the opamps do not need to be switched off during the reset phase of the operation, and hence can be clocked at a high rate. A low-voltage 16 modulator, incorporating pseudodifferential unity-gain-reset opamps, is described. A test chip, realized in a 0.35- m CMOS process and clocked at 10.24 MHz, provided a dynamic range of 80 dB and a signal-to-noise C distortion (SNDR) ratio of 78 dB for a 20-kHz signal bandwidth, and a dynamic range of 74 dB and SNDR of 70 dB for a 50-kHz bandwidth, with a 1-V supply voltage. Index Terms—ADC, charge-pump circuits, delta–sigma, low voltage, sigma–delta, switched-capacitor circuits, switched opamp. I.

Abstract—The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18- m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB. Index Terms—Analog-to-digital converter (ADC), digital calibration, input sampling circuit, opamp-reset switching, pseudodifferential, ultra-low voltage. I.

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6-m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without lowthreshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 0.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW. Index Terms---Analog to digital, low voltage, reliability. I. INTRODUCTION I N mixed-mode analog-to-digital (A/D) interfaces, there are many applications where a video-rate A/D converter (ADC) is integrated with complex digital signal-processing (DSP) blocks in a compatible, low-cost technology---particularly CMOS. Such applications include camcorders, wireless localarea -network transceivers, and digital set-top boxes. Ad...