Results 1  10
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94
A theory of timed automata
, 1999
"... Model checking is emerging as a practical tool for automated debugging of complex reactive systems such as embedded controllers and network protocols (see [23] for a survey). Traditional techniques for model checking do not admit an explicit modeling of time, and are thus, unsuitable for analysis of ..."
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Cited by 1975 (31 self)
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Model checking is emerging as a practical tool for automated debugging of complex reactive systems such as embedded controllers and network protocols (see [23] for a survey). Traditional techniques for model checking do not admit an explicit modeling of time, and are thus, unsuitable for analysis of realtime systems whose correctness depends on relative magnitudes of different delays. Consequently, timed automata [7] were introduced as a formal notation to model the behavior of realtime systems. Its definition provides a simple way to annotate statetransition graphs with timing constraints using finitely many realvalued clock variables. Automated analysis of timed automata relies on the construction of a finite quotient of the infinite space of clock valuations. Over the years, the formalism has been extensively studied leading to many results establishing connections to circuits and logic, and much progress has been made in developing verification algorithms, heuristics, and tools. This paper provides a survey of the theory of timed automata, and their role in specification and verification of realtime systems.
What's Decidable about Hybrid Automata?
 Journal of Computer and System Sciences
, 1995
"... . Hybrid automata model systems with both digital and analog components, such as embedded control programs. Many verification tasks for such programs can be expressed as reachability problems for hybrid automata. By improving on previous decidability and undecidability results, we identify a boundar ..."
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Cited by 266 (14 self)
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. Hybrid automata model systems with both digital and analog components, such as embedded control programs. Many verification tasks for such programs can be expressed as reachability problems for hybrid automata. By improving on previous decidability and undecidability results, we identify a boundary between decidability and undecidability for the reachability problem of hybrid automata. On the positive side, we give an (optimal) PSPACE reachability algorithm for the case of initialized rectangular automata, where all analog variables follow independent trajectories within piecewiselinear envelopes and are reinitialized whenever the envelope changes. Our algorithm is based on the construction of a timed automaton that contains all reachability information about a given initialized rectangular automaton. The translation has practical significance for verification, because it guarantees the termination of symbolic procedures for the reachability analysis of initialized rectangular autom...
A Really Temporal Logic
 Journal of the ACM
, 1989
"... . We introduce a temporal logic for the specification of realtime systems. Our logic, TPTL, employs a novel quantifier construct for referencing time: the freeze quantifier binds a variable to the time of the local temporal context. TPTL is both a natural language for specification and a suitable f ..."
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Cited by 238 (26 self)
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. We introduce a temporal logic for the specification of realtime systems. Our logic, TPTL, employs a novel quantifier construct for referencing time: the freeze quantifier binds a variable to the time of the local temporal context. TPTL is both a natural language for specification and a suitable formalism for verification. We present a tableaubased decision procedure and a model checking algorithm for TPTL. Several generalizations of TPTL are shown to be highly undecidable. 1 Introduction Linear temporal logic is a widely accepted language for specifying properties of reactive systems and their behavior over time [Pnu77, OL82, MP92]. The tableaubased satisfiability algorithm for its propositional version, PTL, forms the basis for the automatic verification and synthesis of finitestate systems [LP84, MW84]. PTL is interpreted over models that abstract away from the actual times at which events occur, retaining only temporal ordering information about the states of a system. The a...
MOCHA: Modularity in Model Checking
, 1998
"... this paper, we describe the toolkit MOCHA in which the proposed approach is being implemented. The input language of MOCHA is a machine readable variant of reactive modules. The following functionalities are currently being supported: ..."
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Cited by 158 (20 self)
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this paper, we describe the toolkit MOCHA in which the proposed approach is being implemented. The input language of MOCHA is a machine readable variant of reactive modules. The following functionalities are currently being supported:
Integration Graphs: A Class of Decidable Hybrid Systems
 In Hybrid Systems, volume 736 of Lecture Notes in Computer Science
, 1993
"... . Integration Graphs are a computational model developed in the attempt to identify simple Hybrid Systems with decidable analysis problems. We start with the class of constant slope hybrid systems (cshs), in which the right hand side of all differential equations is an integer constant. We refer to ..."
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Cited by 67 (9 self)
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. Integration Graphs are a computational model developed in the attempt to identify simple Hybrid Systems with decidable analysis problems. We start with the class of constant slope hybrid systems (cshs), in which the right hand side of all differential equations is an integer constant. We refer to continuous variables whose right hand side constants are always 1 as timers. All other continuous variables are called integrators. The first result shown in the paper is that simple questions such as reachability of a given state are undecidable for even this simple class of systems. To restrict the model even further, we impose the requirement that no test that refers to integrators may appear within a loop in the graph. This restricted class of cshs is called integration graphs . The main results of the paper are that the reachability problem of integration graphs is decidable for two special cases: The case of a single timer and the case of a single test involving integrators. The expres...
Performance analysis of probabilistic timed automata using digital clocks
 Proc. Formal Modeling and Analysis of Timed Systems (FORMATSâ€™03), volume 2791 of LNCS
, 2003
"... ..."
Blackbox conformance testing for realtime systems
 In 11th International SPIN Workshop on Model Checking of Software (SPINâ€™04), volume 2989 of LNCS
, 2004
"... We propose a new framework for blackbox conformance testing of realtime systems. The framework is based on the model of partiallyobservable, nondeterministic timed automata. We argue that partial observability and nondeterminism are essential features for ease of modeling, expressiveness and im ..."
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Cited by 50 (11 self)
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We propose a new framework for blackbox conformance testing of realtime systems. The framework is based on the model of partiallyobservable, nondeterministic timed automata. We argue that partial observability and nondeterminism are essential features for ease of modeling, expressiveness and implementability. The framework allows the user to define, through appropriate modeling, assumptions on the environment of the system under test (SUT) as well as on the interface between the tester and the SUT. We consider two types of tests: analogclock tests and digitalclock tests. Our algorithm to generate analogclock tests is based on an onthefly determinization of the specification automaton during the execution of the test, which in turn relies on reachability computations. The latter can sometimes be costly, thus problematic, since the tester must quickly react to the actions of the system under test. Therefore, we provide techniques which allow analogclock testers to be represented as deterministic timed automata, thus minimizing the reaction time to a simple state jump. We provide algorithms for static or onthefly generation of digitalclock tests. These tests measure time only with finiteprecision, digital clocks, another essential condition for implementability. We also propose a technique for location, edge and state coverage of the specification, by reducing the problem to covering a symbolic reachability graph. This avoids having to generate too many tests. We report on a prototype tool TTG and two case studies: a lighting device and the Bounded Retransmission Protocol. Experimental results obtained by applying TTG on the Bounded Retransmission Protocol show that only a few tests suffice to cover thousands of reachable symbolic states in the specification.
Some progress in the symbolic verification of timed automata
 IN PROC. OF THE 8TH CONFERENCE ON COMPUTERAIDED VERI CATION
, 1997
"... In this paper we discuss the practical difficulty of analyzing the behavior of timed automata and report some results obtained using an experimental bddbased extension of kronos. We have treated examples originating from timing analysis of asynchronous boolean networks and CMOS circuits with delay ..."
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Cited by 49 (4 self)
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In this paper we discuss the practical difficulty of analyzing the behavior of timed automata and report some results obtained using an experimental bddbased extension of kronos. We have treated examples originating from timing analysis of asynchronous boolean networks and CMOS circuits with delay uncertainties and the results outperform those obtained by previous implementations of timed automata verification tools.
ComputerAided Synthesis And Verification Of GateLevel Timed Circuits
, 1995
"... In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to processing and environmental variations, provide component modularity, and lower system power requirement ..."
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Cited by 47 (21 self)
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In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to processing and environmental variations, provide component modularity, and lower system power requirements. Traditional academic asynchronous designs methods use unbounded delay assumptions, resulting in circuits that are verifiable, but ignore timing for simplicity, leading to unnecessarily conservative designs. In industry, however, timing is critical to reduce both chip area and circuit delay. Due to a lack of formal methods that handle timing information correctly, circuits with timing constraints usually require extensive simulation to gain confidence in the design. This thesis bridges this gap by introducing timed circuits in which explicit timing information is incorporated into the specification and utilized throughout the design procedure to optimize the implementation. Our timed circu...
Temporal Proof Methodologies for Timed Transition Systems
 INFORMATION AND COMPUTATION
, 1994
"... We extend the specification language of temporal logic, the corresponding verification framework, and the underlying computational model to deal with realtime properties of reactive systems. The abstract notion of timed transition systems generalizes traditional transition systems conservatively: ..."
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Cited by 44 (8 self)
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We extend the specification language of temporal logic, the corresponding verification framework, and the underlying computational model to deal with realtime properties of reactive systems. The abstract notion of timed transition systems generalizes traditional transition systems conservatively: qualitative fairness requirements are replaced (and superseded) by quantitative lowerbound and upperbound timing constraints on transitions. This framework can model realtime systems that communicate either through shared variables or by message passing and realtime issues such as timeouts, process priorities (interrupts), and process scheduling. We exhibit two styles for the specification of realtime systems. While the first approach uses timebounded versions of the temporal operators, the second approach allows explicit references to time through a special clock variable. Corresponding to the two styles of specification, we present and compare two different proof methodologies for t...