Results 1 
7 of
7
Formal Verification of Synthesized Analog Designs
 In: International Conference on Computer Design
, 1999
"... We present an approach for formal verification of the DC and low frequency behavior of synthesized analog designs containing linear components and components whose behavior can be represented by piecewise linear models. A formal model of the structural description of a synthesized design is extrac ..."
Abstract

Cited by 14 (0 self)
 Add to MetaCart
(Show Context)
We present an approach for formal verification of the DC and low frequency behavior of synthesized analog designs containing linear components and components whose behavior can be represented by piecewise linear models. A formal model of the structural description of a synthesized design is extracted from the sized component netlist produced by the synthesis tool, in terms of characteristic behavior of the components and various voltage and current laws. For the synthesized implementation to be correct, it must imply a formal model extracted from a user given behavior specification. Circuit implementation and expected behavior are both modeled in the PVS higherorder logic proof checker as linear functions and the PVS decision procedures are used to prove the implication. 1 Introduction The challenges in formally verifying an analog design are some what different from those in verifying digital designs. Analog components exhibit continuous time behavior often represented as an...
Combining symbolic simulation and interval arithmetic for the verification of AMS designs
 in: IEEE International Conference on Formal Methods in ComputerAided Design, 2007
"... Abstract—Analog and mixed signal (AMS) designs are important integrated circuits that are usually needed at the interface between the electronic system and the real world. Recently, several formal techniques have been introduced for AMS verification. In this paper, we propose a difference equation ..."
Abstract

Cited by 10 (2 self)
 Add to MetaCart
(Show Context)
Abstract—Analog and mixed signal (AMS) designs are important integrated circuits that are usually needed at the interface between the electronic system and the real world. Recently, several formal techniques have been introduced for AMS verification. In this paper, we propose a difference equations based bounded model checking approach for AMS systems. We define model checking using a combined system of difference equations for both the analog and digital parts, where the state space exploration algorithm is handled with Taylor approximations over interval domains. We illustrate our approach on the verification of several AMS designs including ∆Σ modulator and oscillator circuits. I.
Reachability Analysis Based CircuitLevel Formal Verification
, 2010
"... This dissertation presents a novel verification technique for analog and mixed signal circuits. Analog circuits are widely used in many applications such as consumer electronics, telecommunications, medical electronics, and so on. Furthermore, in deep submicron design, physical effects might underm ..."
Abstract
 Add to MetaCart
(Show Context)
This dissertation presents a novel verification technique for analog and mixed signal circuits. Analog circuits are widely used in many applications such as consumer electronics, telecommunications, medical electronics, and so on. Furthermore, in deep submicron design, physical effects might undermine common digital abstractions of circuit behavior. Therefore, it is necessary to develop systematic methodologies to formally verify hardware design using circuitlevel models. We present a formal method for circuitlevel verification. Our approach is based on translating verification problems to reachability analysis problems. It applies nonlinear ODEs to model circuit dynamics using modified Nodal analysis. Based on the mathematical model, forward reachable regions are computed from given initial states to explore all possible circuit behaviors. Analog properties are checked on all circuit states to ensure fully correctness or find a design flaw. Our specification language extends LTL logic with continuous time and values and applies Brockett annuli to specify analog signals. We also introduced probability into the specification to support practical analog properties such as metastability
ProjectagonBased Reachability Analysis for CircuitLevel Formal Verification
, 2011
"... This dissertation presents a novel verification technique for analog and mixed signal circuits. Analog circuits are widely used in many applications include consumer electronics, telecommunications, medical electronics. Furthermore, in deep submicron design, physical effects might undermine common ..."
Abstract
 Add to MetaCart
(Show Context)
This dissertation presents a novel verification technique for analog and mixed signal circuits. Analog circuits are widely used in many applications include consumer electronics, telecommunications, medical electronics. Furthermore, in deep submicron design, physical effects might undermine common digital abstractions of circuit behavior. Therefore, it is necessary to develop systematic methodologies to formally verify hardware design using circuitlevel models. We present a formal method for circuitlevel verification. Our approach is based on translating verification problems to reachability analysis problems. It applies nonlinear ODEs to model circuit dynamics using modified nodal analysis. Forward reachable regions are computed from given initial states to explore all possible circuit behaviors. Analog properties are checked on all circuit states to ensure full correctness or find a design flaw. Our specification language extends LTL logic with continuous time and values and applies Brockett’s annuli to specify analog signals. We also introduced probability into the specification to support practical analog properties such as metastability behavior.