We present an approach for formal verification of the DC and low frequency behavior of synthesized analog designs containing linear components and components whose behavior can be represented by piecewise linear models. A formal model of the structural description of a synthesized design is extracted from the sized component netlist produced by the synthesis tool, in terms of characteristic behavior of the components and various voltage and current laws. For the synthesized implementation to be correct, it must imply a formal model extracted from a user given behavior specification. Circuit implementation and expected behavior are both modeled in the PVS higher-order logic proof checker as linear functions and the PVS decision procedures are used to prove the implication. 1 Introduction The challenges in formally verifying an analog design are some what different from those in verifying digital designs. Analog components exhibit continuous time behavior often represented as an...