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53
From Control Flow to Dataflow
, 1989
"... Are imperative languages tied inseparably to the von Neumann model or can they be implemented in some natural way on dataflow architectures? In this paper, we show how imperative language programs can be translated into dataflow graphs and executed on a dataflow machine like Monsoon. This translatio ..."
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Cited by 22 (4 self)
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Are imperative languages tied inseparably to the von Neumann model or can they be implemented in some natural way on dataflow architectures? In this paper, we show how imperative language programs can be translated into dataflow graphs and executed on a dataflow machine like Monsoon. This translation can exploit both finegrain and coarsegrain parallelism in imperative language programs. More importantly, we establish a close connection between our work and current research in the imperative languages community on data dependences, control dependences, program dependence graphs, and static single assignment form. These results suggest that data ow graphs can serve as an executable intermediate representation in parallelizing compilers.
Diagnostic Fault Equivalence Identification Using Redundancy Information Structural Analysis
 Information & Structural Analysis,” in Proc. International Test Conf
, 1996
"... A significant problem with current diagnostic test generation techniques is the time spent in identifying diagnostic equivalences amongst fault pairs. Fault pair distance analysis is introduced in this paper to characterize diagnostically equivalent fault pairs and motivate local circuit transformat ..."
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Cited by 19 (7 self)
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A significant problem with current diagnostic test generation techniques is the time spent in identifying diagnostic equivalences amongst fault pairs. Fault pair distance analysis is introduced in this paper to characterize diagnostically equivalent fault pairs and motivate local circuit transformations and structural analysis to identify equivalences in combinational circuits rapidly. Our results establish a connection between redundant faults and a specific class of diagnostically equivalent fault pairs. Structural analysis is then used to identify equivalences between fault pairs. Experimental results are presented on benchmark circuits to demonstrate the efficiency of the techniques. 1 Introduction Fault diagnosis aims at locating failures in chips that have been identified as defective. Previous diagnosis research can be classified into two major areas: causeeffect analysis techniques [14] and effectcause analysis techniques [5, 6]. Causeeffect techniques rely on storing sym...
A Linear Algorithm for Analysis of Minimum Spanning and Shortest Path Trees of Planar Graphs
 Algorithmica
, 1992
"... We give a linear time and space algorithm for analyzing trees in planar graphs. The algorithm can be used to analyze the sensitivity of a minimum spanning tree to changes in edge costs, to find its replacement edges, and to verify its minimality. It can also be used to analyze the sensitivity of a s ..."
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Cited by 17 (0 self)
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We give a linear time and space algorithm for analyzing trees in planar graphs. The algorithm can be used to analyze the sensitivity of a minimum spanning tree to changes in edge costs, to find its replacement edges, and to verify its minimality. It can also be used to analyze the sensitivity of a singlesource shortest path tree to changes in edge costs, and to analyze the sensitivity of a minimum cost network flow. The algorithm is simple and practical. It uses the properties of a planar embedding, combined with a heapordered queue data structure. Let G = (V; E) be a planar graph, either directed or undirected, with n vertices and m = O(n) edges. Each edge e 2 E has a realvalued cost cost(e). A minimum spanning tree of a connected, undirected planar graph G is a spanning tree of minimum total edge cost. If G is directed and r is a vertex from which all other vertices are reachable, then a shortest path tree from r is a spanning tree that contains a minimumcost path from r to every...
A New, Simpler LinearTime Dominators Algorithm
 ACM Transactions on Programming Languages and Systems
, 1998
"... this article is organized as follows. Section 2 outlines Lengauer and Tarjan's approach. Section 3 gives a broad overview of our algorithm and dierentiates it from previous work. Section 4 presents our algorithm in detail, and Section 5 analyzes its running time. Section 6 presents our new path ..."
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Cited by 15 (4 self)
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this article is organized as follows. Section 2 outlines Lengauer and Tarjan's approach. Section 3 gives a broad overview of our algorithm and dierentiates it from previous work. Section 4 presents our algorithm in detail, and Section 5 analyzes its running time. Section 6 presents our new pathcompression result, on which the analysis relies. Section 7 describes our implementation, and Section 8 reports experimental results. We conclude in Section 9
Dynamic searchspace pruning techniques in path sensitization
 in Design Automation Conf
, 1994
"... Abstract — A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path sensitization can be posed as a search, in the ndimensional Boolean space, for a consistent assignment of l ..."
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Cited by 14 (4 self)
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Abstract — A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path sensitization can be posed as a search, in the ndimensional Boolean space, for a consistent assignment of logic values to the circuit nodes which also satisfies a given condition. In this paper we propose and demonstrate the effectiveness of several new techniques for searchspace pruning for test pattern generation. In particular, we present lineartime algorithms for dynamically identifying unique sensitization points and for dynamically maintaining reduced head line sets. In addition, we present two powerful mechanisms that drastically reduce the number of backtracks: failuredriven assertions and dependencydirected backtracking. Both mechanisms can be viewed as a form of learning while searching and have analogs in other application domains. These search pruning methods have been implemented in a generic path sensitization engine called LEAP. A test pattern generator, TGLEAP, that uses this engine was also developed. We present experimental results that compare the effectiveness of our proposed search pruning strategies to those of PODEM, FAN, and SOCRATES. In particular, we show that LEAP is very efficient in identifying undetectable faults and in generating tests for difficult faults. I.
Time Efficient Automatic Test Pattern Generation Systems
, 1994
"... Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits. Due to the complexity of very large scale integrated circuits, such systems are essential for achieving tests with high fault coverage. This thesis presents time efficient ATPG systems for combinati ..."
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Cited by 13 (0 self)
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Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits. Due to the complexity of very large scale integrated circuits, such systems are essential for achieving tests with high fault coverage. This thesis presents time efficient ATPG systems for combinational and sequential circuits. First, a fast, effective deterministic test generation algorithm provides a time efficient ATPG system for combinational circuits. This algorithm utilizes a new fast fault simulation algorithm, Parallel Pattern Critical Path Tracing (PPCPT). At the earlier stages of test set simulation, PPCPT takes advantage of critical path tracing, then dynamically transforms to parallel pattern single fault propagation as the simulation progresses. Further, for concurrent engineering design environments, an incremental ATPG concept is introduced. When there is a small circuit modification, incremental test generation utilizes information from tests for the original circuit to...
Implication and Evaluation Techniques for Proving Fault Equivalence
 in Proc. 17th IEEE VLSI Test Symp
, 1999
"... Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluatio ..."
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Cited by 12 (2 self)
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Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence. 1 Introduction Recent literature on diagnosis [1, 2] shows that a significant fraction of fault pairs that remain indistinguished after applying a complete fault detection test set are, in fact, equivalent. Thus, diagnostic test pattern generators spend considerable effort on attempting to distinguish indistinguishable fault pairs. The problem of identifying fault equivalence of a fault pair in diagno...
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction
 In Proceedings of the 19th IEEE VLSI Test Symposium
, 2001
"... A procedure for identifying functionally equivalent faults and improving the performance of diagnostic test pattern generation is described in this paper. The procedure is based on evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redund ..."
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Cited by 8 (1 self)
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A procedure for identifying functionally equivalent faults and improving the performance of diagnostic test pattern generation is described in this paper. The procedure is based on evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Equivalence is proved without the previously required circuit transformations. Stembranch equivalences for reconvergent stems and their branches are identified efficiently obviating the need to check for nonmasking and multiplepath sensitization. Both static and dynamic techniques are developed to exploit relations among inputs of dominator cones. This reduces the simulation time required by the procedure and enables evaluation of larger cones than could be evaluated earlier. As a result, more equivalent fault pairs are identified. Experiments performed on ISCAS85 circuits and full scan ISCAS89 circuits are used to demonstrate the effectiveness of the proposed techniques. 1
Automatic Generation Of DataFlow Analyzers: A Tool For Building Optimizers
, 1993
"... Modern compilers generate good code by performing global optimizations. Unlike other functions of the compiler such as parsing and code generation which examine only one statement or one basic block at a time, optimizers examine large parts of a program and coordinate changes in widely separated par ..."
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Cited by 8 (0 self)
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Modern compilers generate good code by performing global optimizations. Unlike other functions of the compiler such as parsing and code generation which examine only one statement or one basic block at a time, optimizers examine large parts of a program and coordinate changes in widely separated parts of a program. Thus optimizers use more complex data structures and consume more time. To generate the best code, optimizers perform not one global transformation, but many in concert. These transformations can interact in unforeseen ways. This dissertation concerns the building of optimizers that are modular and extensible. It espouses an optimizer architecture, first proposed by Kildall, in which each phase is based on a dataflow analysis (DFA) of the program and on an optimization function that transforms the program. To support the architecture, a set of abstractionsflow values, flow functions, path simplification rules, action routinesis provided. A tool called Sharlit turns a DFA specification consisting of these abstractions into a solver for a DFA problem. At the heart of Sharlit is an algorithm called path simplification, an extension of Tarjan's fast path algorithm. Path simplification unifies several powerful DFA solution techniques. By using path simplification rules, compiler writers can construct a wide range of dataflow analyzers, from simple iterative ones, to solvers that use local analysis, interval analysis, or sparse dataflow evaluation. Sharlit frees compiler writers from the details of how these various solution techniques. The compiler writer can view the program representation as a simple flow graph in which each instruction is a node. Data structures to represent basic blocks and other regions are automatically generated. Sharlit promotes ...