A significant problem with current diagnostic test generation techniques is the time spent in identifying diagnostic equivalences amongst fault pairs. Fault pair distance analysis is introduced in this paper to characterize diagnostically equivalent fault pairs and motivate local circuit transformations and structural analysis to identify equivalences in combinational circuits rapidly. Our results establish a connection between redundant faults and a specific class of diagnostically equivalent fault pairs. Structural analysis is then used to identify equivalences between fault pairs. Experimental results are presented on benchmark circuits to demonstrate the efficiency of the techniques. 1 Introduction Fault diagnosis aims at locating failures in chips that have been identified as defective. Previous diagnosis research can be classified into two major areas: cause-effect analysis techniques [1--4] and effect-cause analysis techniques [5, 6]. Cause-effect techniques rely on storing sym...

We give a linear time and space algorithm for analyzing trees in planar graphs. The algorithm can be used to analyze the sensitivity of a minimum spanning tree to changes in edge costs, to find its replacement edges, and to verify its minimality. It can also be used to analyze the sensitivity of a singlesource shortest path tree to changes in edge costs, and to analyze the sensitivity of a minimum cost network flow. The algorithm is simple and practical. It uses the properties of a planar embedding, combined with a heap-ordered queue data structure. Let G = (V; E) be a planar graph, either directed or undirected, with n vertices and m = O(n) edges. Each edge e 2 E has a real-valued cost cost(e). A minimum spanning tree of a connected, undirected planar graph G is a spanning tree of minimum total edge cost. If G is directed and r is a vertex from which all other vertices are reachable, then a shortest path tree from r is a spanning tree that contains a minimum-cost path from r to every...

this article is organized as follows. Section 2 outlines Lengauer and Tarjan's approach. Section 3 gives a broad overview of our algorithm and dierentiates it from previous work. Section 4 presents our algorithm in detail, and Section 5 analyzes its running time. Section 6 presents our new path-compression result, on which the analysis relies. Section 7 describes our implementation, and Section 8 reports experimental results. We conclude in Section 9

Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits. Due to the complexity of very large scale integrated circuits, such systems are essential for achieving tests with high fault coverage. This thesis presents time efficient ATPG systems for combinational and sequential circuits. First, a fast, effective deterministic test generation algorithm provides a time efficient ATPG system for combinational circuits. This algorithm utilizes a new fast fault simulation algorithm, Parallel Pattern Critical Path Tracing (PPCPT). At the earlier stages of test set simulation, PPCPT takes advantage of critical path tracing, then dynamically transforms to parallel pattern single fault propagation as the simulation progresses. Further, for concurrent engineering design environments, an incremental ATPG concept is introduced. When there is a small circuit modification, incremental test generation utilizes information from tests for the original circuit to...

Modern compilers generate good code by performing global optimizations. Unlike other functions of the compiler such as parsing and code generation which examine only one statement or one basic block at a time, optimizers examine large parts of a program and coordinate changes in widely separated parts of a program. Thus optimizers use more complex data structures and consume more time. To generate the best code, optimizers perform not one global transformation, but many in concert. These transformations can interact in unforeseen ways. This dissertation concerns the building of optimizers that are modular and extensible. It espouses an optimizer architecture, first proposed by Kildall, in which each phase is based on a data-flow analysis (DFA) of the program and on an optimization function that transforms the program. To support the architecture, a set of abstractions---flow values, flow functions, path simplification rules, action routines---is provided. A tool called Sharlit turns a DFA specification consisting of these abstractions into a solver for a DFA problem. At the heart of Sharlit is an algorithm called path simplification, an extension of Tarjan's fast path algorithm. Path simplification unifies several powerful DFA solution techniques. By using path simplification rules, compiler writers can construct a wide range of data-flow analyzers, from simple iterative ones, to solvers that use local analysis, interval analysis, or sparse data-flow evaluation. Sharlit frees compiler writers from the details of how these various solution techniques. The compiler writer can view the program representation as a simple flow graph in which each instruction is a node. Data structures to represent basic blocks and other regions are automatically generated. Sharlit promotes ...

Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence. 1 Introduction Recent literature on diagnosis [1, 2] shows that a significant fraction of fault pairs that remain indistinguished after applying a complete fault detection test set are, in fact, equivalent. Thus, diagnostic test pattern generators spend considerable effort on attempting to distinguish indistinguishable fault pairs. The problem of identifying fault equivalence of a fault pair in diagno...

A procedure for identifying functionally equivalent faults and improving the performance of diagnostic test pattern generation is described in this paper. The procedure is based on evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Equivalence is proved without the previously required circuit transformations. Stem-branch equivalences for reconvergent stems and their branches are identified efficiently obviating the need to check for non-masking and multiple-path sensitization. Both static and dynamic techniques are developed to exploit relations among inputs of dominator cones. This reduces the simulation time required by the procedure and enables evaluation of larger cones than could be evaluated earlier. As a result, more equivalent fault pairs are identified. Experiments performed on ISCAS85 circuits and full scan ISCAS89 circuits are used to demonstrate the effectiveness of the proposed techniques. 1

Identifying some pointers as invisible threads, for the purposes of storage management, is a generalization from several widely used programming conventions, like threaded trees. The necessary invariant is that nodes that are accessible (without threads) emit threads only to other accessible nodes. Dynamic tagging or static typing of threads ameliorates storage recycling both in functional and imperative languages. We have seen the distinction between threads and links sharpen both hardware- and software-supported storage management in Scheme, and also in C. Certainly, therefore, implementations of languages that already have abstract management and concrete typing, should detect and use this as a new static type. Categories and subject descriptors: D.3.3 [Programming Languages]: Language Constructs and Features---data types and structures, dynamic storage management, abstract data types; E.2 [Data Storage Representations ]: Linked representations; B.3.2 [Memory Structures]: Design S...

Abstract. The computation of dominators in a flowgraph has applications in program optimization, circuit testing, and other areas. Lengauer and Tarjan [17] proposed two versions of a fast algorithm for finding dominators and compared them experimentally with an iterative bit vector algorithm. They concluded that both versions of their algorithm were much faster than the bit-vector algorithm even on graphs of moderate size. Recently Cooper et al. [9] have proposed a new, simple, tree-based iterative algorithm. Their experiments suggested that it was faster than the simple version of the Lengauer-Tarjan algorithm on graphs representing computer program control flow. Motivated by the work of Cooper et al., we present an experimental study comparing their algorithm (and some variants) with careful implementations of both versions of the Lengauer-Tarjan algorithm and with a new hybrid algorithm. Our results suggest that, although the performance of all the algorithms is similar, the most consistently fast are the simple Lengauer-Tarjan algorithm and the hybrid algorithm, and their advantage increases as the graph gets bigger or more complicated. 1

. Recently it has been discovered that control flow graphs of structured programs have bounded treewidth. In this paper we show that this knowledge can be used to design fast algorithms for control flow analysis. We give a linear time algorithm for the problem of finding the immediate multiple-vertex dominator set for all nodes in a control flow graph. The problem was originally proposed by Gupta (Generalized dominators and post-dominators, ACM Symp. on Principles of Programming Languages, 1992). Without the restriction of bounded treewidth the fastest algorithm runs in O(jV j jEj) on a graph with jV j nodes and jEj edges and is due to Alstrup, Clausen and Jørgensen (An O(jV j jEj) Algorithm for Finding Immediate Multiple-Vertex Dominators, accepted to Information Processing Letters). 1 Introduction Constructing dominator trees for control flow graphs G(V; E; s) has been investigated in many papers (see e.g. [8, 9, 11, 13, 14]) in connection with global flow analysis and program op...