Evolvable hardware (EHW) has attracted increasing attention since early 1990's with the advent of easily reconfigurable hardware such as field programmable gate arrays (FPGAs). It promises to provide an entirely new approach to complex electronic circuit design and new adaptive hardware. EHW has been demonstrated to be able to perform a wide range of tasks from pattern recognition to adaptive control. However, there are still many fundamental issues in EHW which remain open. This paper reviews the current status of EHW, discusses the promises and possible advantages of EHW, and indicates the challenges we must meet in order to develop practical and large-scale EHW. 1 Introduction Evolvable hardware (EHW) refers to hardware that can change its architecture and behaviour dynamically and autonomously by interacting with its environment. At present, almost all EHW uses an evolutionary algorithm (EA) as their main adaptive mechanism. One of the key motivations behind EHW is to learn from N...

Our experiences with a range of evolutionary robotic experiments have resulted in major changes to our set-up of artificial life experiments and our interpretation of observed phenomena. Initially, we investigated simulation-reality relationships in order to transfer our artificial life simulation work with evolution of neural network agents to real robots. This is a difficult task, but can, in a lot of cases, be solved with a carefully built simulator. By being able to evolve control mechanisms for physical robots, we were able to study biological hypotheses about animal behaviours by using exactly the same experimental set-ups as were used in the animal behavioural experiments. Evolutionary robotic experiments with rats open field box experiments and chick detours show how evolutionary robotics can be a powerful biological tool, and they also suggest that incremental learning might be fruitful for achieving complex robot behaviour in an evolutionary context. However, it is not enough...

Our previous work focused on the synthesis of sequential circuits based on a partial input/output sequence. As the behavioural description of the target circuit is not known the correctness of the result can not be verified. This paper proposes a method which increases the correctness percentage of the finite-state machine (FSM) synthesis using multiple partial input/output sequences. The synthesizer is based on Genetic Algorithm. The experimental results show that the correctness percentage can be increased to 100% by increasing of the number of input/output sequences.

The scalability problem is a major impediment to the use of hardware evolution for real-world circuit design problems. A potential solution is to model the map between genotype and phenotype on biological development. Although development has been shown to improve scalability for a few toy problems, it has not been demonstrated for any circuit design problems. This paper presents such a demonstration for two problems, the n-bit adder with carry and even n-bit parity problems, and shows that development imposes, and benefits from, fewer constraints on evolutionary innovation than other approaches to scalability. 1.

. 1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in first time. The new representation of logic gate in extrinsic EHW allows us to describe behaviour of any multi-input multi-output logic function. The circuit is represented in the form of connections and functionalities of a rectangular array of building blocks. Each building block can implement primitive logic function or any multi-input multioutput logic function defined in advance. The method has been tested on evolving logic circuits using half adder, full adder and multiplier. The effectiveness of this approach is investigated for multiple-valued and binary arithmetical functions. For these functions either method appears to be much more efficient than similar approach with two-input one-output cell representation. 1 Introduction Evolvable Hardware (EHW) is technique to synthesize electronic circuits using genetic algorithms. ...

Abstract. This paper focuses on characteristics and applications of evolvable hardware (EHW) to space systems. The motivation for looking at EHW originates in the need for more autonomous adaptive space systems. The idea of evolvable hardware becomes attractive for long missions when the hardware looses optimality, and uploading new software only partly alleviates the problem if the computing hardware becomes obsolete or the sensing hardware faces needs outside original design specifications. The paper reports the first intrinsic evolution on an analog ASIC (a custom analog neural chip), suggests evolution of dynamical systems in state-space representations, and demonstrates evolution of compression algorithms with results better than the best-known compression algorithms. 1

: Evolvable hardware is a new technology, where circuit connection is subject to evolution. The model of the evolvable circuit is used in the task of image compression. This work is done with evolvable hardware at functional level. Possible hardware implementations are discussed and a new concept of constrained evolution --- pseudo evolvable hardware --- is open. This paper describes the implementation principle of a virtual evolvable machine on top of a normal FPGA. In this way, the current FPGAs can implement evolvable circuit. Copyright c fl2000 IFAC Keywords: configuration, genetic algorithms, digital circuits, self-optimizing systems, system concepts. 1. INTRODUCTION Let us discuss this task: some circuit, implementing the function of m inputs and n outputs, is needed. Desired function is unknown at the time of design and additionally it can change in order to adapt to the environment changes during the circuit execution. It means, that a real-time modifying hardware arc...

Our previous work focused on the synthesis of sequential circuits based on a partial input/output sequence. As the behavioural description of the target circuit is not known the correctness of the result can not be verified. This paper proposes a method which increases the correctness percentage of the finite-state machine (FSM) synthesis using multiple partial input/output sequences. The synthesizer is based on Genetic Algorithm. The experimental results show that the correctness percentage can be increased to 100% by increasing of the number of input/output sequences. 1. Introduction A finite-state machine (FSM) can be constructed from the understanding of its behavior. Each state must be identified to define the state transition function and the output function. Given a behavioral description, the target FSM can be synthesized by many conventional methods. In contrast, this paper proposes a different approach: an FSM is synthesized not from a behavioural description but from part...

Remarkable advantages of asynchronous circuits in comparison with their synchronous counterparts results in vast effort in designing such circuits. This paper proposes optimized asynchronous circuit design approach by exploiting potent evolutionary circuit design method. The evolutionary algorithm applies fast and accurate hazard detection technique as a fitness function. Outcomes of proposed method in designing fundamental mode asynchronous circuit in comparison with previous methodologies reveal its notable advantages like, multi level circuit design with lower number of gates which results in lower area, lower power consumption and lower cost. Experimental result demonstrate that the proposed method reduces number of gates about