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38
Performance Analysis of Embedded Software Using Implicit Path Enumeration
, 1995
"... Embedded computer systems are characterized by the presence of a processor running application specific software. A large number of these systems must satisfy realtime constraints. This paper examines the problem of determining the bound on the running time of a given program on a given processor. ..."
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Cited by 169 (1 self)
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Embedded computer systems are characterized by the presence of a processor running application specific software. A large number of these systems must satisfy realtime constraints. This paper examines the problem of determining the bound on the running time of a given program on a given processor. An important aspect of this problem is determining the extreme case program paths. The state of the art solution here relies on an explicit enumeration of program paths. This runs out of steam rather quickly since the number of feasible program paths is typically exponential in the size of the program. We present a solution for this problem, which considers all paths implicitly by using integer linear programming. This solution is implemented in the program cinderella which currently targets a popular embedded processor  the Intel i960. The preliminary results of using this tool are presented here.
A General Probabilistic Framework for Worst Case Timing Analysis
, 2002
"... The traditional approach to worstcase statictiming analysis is becoming unacceptably conservative due to an everincreasing number of circuit and process effects. We propose a fundamentally different framework that aims to significantly improve the accuracy of timing predictions through fully prob ..."
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Cited by 73 (4 self)
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The traditional approach to worstcase statictiming analysis is becoming unacceptably conservative due to an everincreasing number of circuit and process effects. We propose a fundamentally different framework that aims to significantly improve the accuracy of timing predictions through fully probabilistic analysis of gate and path delays. We describe a bottomup approach for the construction of joint probability density function of path delays, and present novel analytical and algorithmic methods for finding the full distribution of the maximum of a random path delay space with arbitrary path correlations.
Statistical Delay Calculation, a Linear Time Method
, 1997
"... This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) ..."
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Cited by 39 (1 self)
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This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new approximate scheme to perform the delay calculations with stochastic delay values in linear time. The results are validated with Monte Carlo simulations. From a mathematical analysis some counterintuitive properties of delays in the presence of uncertain delay values are shown. The results section shows that that traditional worstcase timing analysis is on average 21% too pessimistic for the set of IWLS '91 combinational benchmark circuits for a given delay model. Also, it is shown that the traditional typical delay calculation underestimates the most likely circuit delay by 0  14%. Furthermore, due to the mathematical properties of the delay...
Fast statistical timing analysis handling arbitrary delay correlations
 in Proc. IEEE/ACM Design Autom. Conf
"... An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire cumulative distribution function of the circuit delay using a new mathematical formulation. Spatial as well as structural c ..."
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Cited by 34 (2 self)
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An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire cumulative distribution function of the circuit delay using a new mathematical formulation. Spatial as well as structural correlations between gate and wire delays can be taken into account. The algorithm can handle node delays described by nonGaussian distributions. Because the analytical computation of an exact cumulative distribution function for a probabilistic graph with arbitrary distributions is infeasible, we find tight upper and lower bounds on the true cumulative distribution. An efficient algorithm to compute the bounds is based on a PERTlike single traversal of the subgraph containing the set of N deterministically longest paths. The efficiency and accuracy of the algorithm is demonstrated on a set of ISCASâ€™85 benchmarks. Across all the benchmarks, the average rms error between the exact distribution and lower bound is 0.7%, and the average maximum error at 95 th percentile is 0.6%. The computation of bounds for the largest benchmark takes 39 seconds.
Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms
 IEEE TRANSACTIONS ON CAD
, 1993
"... This paper addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be unknown when a vector is applied at5 the inputs.) It is well known that using the length of the topologic ..."
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Cited by 34 (1 self)
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This paper addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be unknown when a vector is applied at5 the inputs.) It is well known that using the length of the topologically longest path as an estimate of circuit delay may be pessimistic since this path may be false, i.e., it cannot propagate an event. Thus, the true delay corresponds to the length of the longest true path. This forces us to examine the conditions under which a path is true. We introduce the notion of static cosensitization of paths which leads us to necessary and sufficient conditions for determining the truth or falsity of a single path, or a set of paths. We apply these results to develop a delay computation algorithm that has the unique feature that it is able to determine the truth or falsity of entire sets of paths simultaneously. This algorithm uses conventional stuckatfault testing techniques to arrive at a delay computation method that is both correct and computationally practical, even for particularly difficult circuits.
SkewTolerant Circuit Design
, 1999
"... As cycle times in highperformance digital systems shrink faster than simple process improvement allows, sequencing overhead consumes an increasing fraction of the clock period. In particular, the overhead of traditional domino pipelines can consume 25% or more of the cycle time in aggressive system ..."
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Cited by 23 (2 self)
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As cycle times in highperformance digital systems shrink faster than simple process improvement allows, sequencing overhead consumes an increasing fraction of the clock period. In particular, the overhead of traditional domino pipelines can consume 25% or more of the cycle time in aggressive systems. Fortunately, the designer can hide much of this overhead through better design techniques. The key to skewtolerant design is avoiding hard edges in which data must setup before a clock edge but will not continue propagating until after the clock edge. Skewtolerant domino circuits use multiple overlapping clocks to eliminate latches, removing hard edges and hiding the sequencing overhead.
Logic Design Error Diagnosis and Correction
 IEEE Transactions on VLSI Systems
, 1994
"... She's the neighbor dog who's courting my dog. ..."
Statistical Timing Analysis Using Bounds
 ACM/IEEE Design, Automation and Test in Europe Conference and Exhibition
, 2003
"... The gr wing impact of withindieprthin varE9]CM hascrM:]E the needfor statistical timing analysis,wher gate delaysar modeled asrME]9 varC[j9Mk Statistical timing analysis hastr:)):)Mk)G4 sufferE fr exponentialrp time complexity withcirM:: size, due to the dependenciescrpend byrMj[ ver ging paths in ..."
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Cited by 15 (0 self)
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The gr wing impact of withindieprthin varE9]CM hascrM:]E the needfor statistical timing analysis,wher gate delaysar modeled asrME]9 varC[j9Mk Statistical timing analysis hastr:)):)Mk)G4 sufferE fr exponentialrp time complexity withcirM:: size, due to the dependenciescrpend byrMj[ ver ging paths in thecir:[jE In thispaper , weprEG)9 a newappr:9M to statistical timing analysis which uses statistical bounds.Firds we pr vide afor9[ definition of the statistical delay of acirC:[ and der ve a statistical timing analysis methodfrh this definition. Since this methodfor finding the exact statistical delay has exponentialrp time complexity with cir cuit size, we alsoproMjC a new methodfor computing statistical bounds which haslinear rn time complexity. Wepr ve thecor:]CE ness of theprME9[: bounds. Since we pr vide both a lower and upper bound on the trM statistical delay, we candeter9C: the quality of the bounds. TheprMjjGG methodswer implemented and tested onbenchmar cirhmar ThereMj]9 demonstrk: that the prM posed bounds have only a small erll .
A Statistical Gatedelay Model Considering Intragate Variability
 in Proc. Int. Conf. Computer Aided Design
, 2003
"... This paper proposes a model for calculating statistical gatedelay variation caused by intrachip and interchip variability. As the variation of individual gate delays directly influences the circuitdelay variation, it is important to characterize each gatedelay variation accurately. Furthermore, ..."
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Cited by 10 (0 self)
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This paper proposes a model for calculating statistical gatedelay variation caused by intrachip and interchip variability. As the variation of individual gate delays directly influences the circuitdelay variation, it is important to characterize each gatedelay variation accurately. Furthermore, as every transistor in a gate affects the transient characteristics of the gate, it is also necessary to consider the intragate variability in the model of gatedelay variation. This effect is not captured in existing statistical delay analyses. The proposed model considers the intragate variability through the introduction of sensitivity constants. The accuracy of the model is evaluated, and some simulation results for circuit delay variation are presented. 1.