analog-to-digital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18- m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mmP and dissipates 98 mW. Index Terms—Analog integrated circuits, capacitor mismatch, comparator sharing, discrete-time common-mode voltage regulation, early comparison, low power, low voltage, nested CMOS gain boosting, opamp sharing, passive capacitor error-averaging, pipeline analog-to-digital converter, pseudo-differential, subsampling. I.

A 1.2V switched-capacitor sigma-delta modulator achieves 96dB peak SFDR and 84dB peak SNDR at 1MS/s in 2 4

: An operational amplifier designed with 0.35um CMOS technology is presented. All the transistors are realized with minimum or near-minimum channel length. As the short channel length causes performance degradation, a proper operational amplifier structure is selected to compensate the performance degradation. The op amp is designed to meet the requirement of high-speed high-resolution sigma delta modulators. It has a folded-cascode first stage and a class-A output stage. It features a DC gain of 78dB, an openloop unity-gain frequency of 266MHZ, a slew rate of 650V/us, and consumes 10.2mW from a +/-1.5V power supply. High level simulation is used to evaluate the OTA performance in sigma delta modulators. 1. INTRODUCTION The fast development of CMOS process technique makes it possible to integrate more and more functions into a single Digital-signal-Processing chip. However, the physical signal (which is analog) still needs an interface to be handled by DSP. A/D and D/A converters are...

Abstract—This paper presents the design and experimental results of a continuous-time 61 modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time 61 modulators is solved by our proposed architecture. A prototype third-order continuous-time 61 modulator with 5-bit internal quantization was realized in a 0.5- m double-poly triple-metal CMOS technology, with a chip area of 2.4 2.4 mm2. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply. Index Terms—Analog-to-digital conversion, CMOS analog integrated circuits, continuous-time 61 modulation, multibit internal quantization. I.

submitted by

Abstract not found

This material is posted here with permission of the IEEE.