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Efficient thermal placement of standard cells in 3d ics using a force directed approach
 Proc. ICCAD 2003
"... As the technology node progresses, thermal problems are becoming more prominent especially in the developing technology of threedimensional (3D) integrated circuits. The thermal placement method presented in this paper uses an iterative forcedirected approach in which thermal forces direct cells a ..."
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Cited by 93 (14 self)
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As the technology node progresses, thermal problems are becoming more prominent especially in the developing technology of threedimensional (3D) integrated circuits. The thermal placement method presented in this paper uses an iterative forcedirected approach in which thermal forces direct cells away from areas of high temperature. Finite element analysis (FEA) is used to calculate temperatures efficiently during each iteration. Benchmark circuits produce thermal placements with both lower temperatures and thermal gradients while wirelength is minimally affected. 1.
Fastplace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model
, 2004
"... Abstract — In this paper, we present FastPlace – a fast, iterative, flat placement algorithm for largescale standard cell designs. FastPlace is based on the quadratic placement approach. The quadratic approach formulates the wirelength minimization problem as a convex quadratic program that can be ..."
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Cited by 75 (8 self)
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Abstract — In this paper, we present FastPlace – a fast, iterative, flat placement algorithm for largescale standard cell designs. FastPlace is based on the quadratic placement approach. The quadratic approach formulates the wirelength minimization problem as a convex quadratic program that can be solved efficiently by some analytical techniques. However it suffers from some drawbacks. First, the resulting placement has a lot of overlap among cells. Second, the resulting total wirelength may be long as the quadratic wirelength objective is only an indirect measure of the linear wirelength. Third, existing net models tend to create a lot of nonzero entries in the connectivity matrix that slows down the quadratic program solver. To handle the above problems we propose: (1) An efficient Cell Shifting technique to remove cell overlap from the quadratic program solution and also accelerate the convergence of the solver. This technique produces a global placement with even cell distribution in a very short time. (2) An Iterative Local Refinement technique to reduce the wirelength according to the halfperimeter measure. (3) A Hybrid Net Model that is a combination of the traditional clique and star models. This net model greatly reduces the number of nonzero entries in the connectivity matrix and results in a significant speedup of the solver. Experimental results show that FastPlace is on average 13.4, 102
Combinatorial Techniques for Mixedsize Placement
 ACM TRANS. ON DESIGN AUTOM. OF ELEC. SYS
, 2005
"... ..."
Smoothening Maxterms and Analytical Minimization of HalfPerimeter Wirelength
"... This work addresses a class of optimization problems arising in engineering, where the objective function contains nondi erentiabilities, and yet needs to be minimized analytically. While large classes of nondi erentiabilities can be successfully smoothened by approximations, existing techniques f ..."
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Cited by 4 (0 self)
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This work addresses a class of optimization problems arising in engineering, where the objective function contains nondi erentiabilities, and yet needs to be minimized analytically. While large classes of nondi erentiabilities can be successfully smoothened by approximations, existing techniques fail to provide a symmetric, smooth and computationally convenient approximation for the multivariate max function with provable properties. Our work proposes such an approximation and immediately applies it to a hypergraph placement problem, previously addressed by heuristic transformation of hypergraphs into graphs. Empirical validation is performed by comparing our implementations to several optimal but unacceptably laborious methods, including network ows and linear programming with CPLEX.
Efficient Optimization by Modifying the Objective Function: Applications to TimingDriven VLSI Layout
 IEEE Trans. on Circuits and Systems
, 2001
"... When minimizing a given objective function is challenging because of, for example, combinatorial complexity or points of nondifferentiability, one can apply more efficient and easiertoimplement algorithms to modified versions of the function. In the ideal case, one can employ known algorithms for ..."
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Cited by 3 (0 self)
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When minimizing a given objective function is challenging because of, for example, combinatorial complexity or points of nondifferentiability, one can apply more efficient and easiertoimplement algorithms to modified versions of the function. In the ideal case, one can employ known algorithms for the modified function that have a thorough theoretical and empirical record and for which public implementations are available. The main requirement here is that minimizers of the objective function not change much through the modification, i.e., the modification must have a bounded effect on the quality of the solution. Review of classic and recent placement algorithms suggests a dichotomy between approaches that either (a) heuristically minimize a potentially irrelevant objective function (e.g., VLSI placement with quadratic wirelength) motivated by the simplicity and speed of a standard minimization algorithm, or (b) devise elaborate problemspecific minimization heuristics for more relevant objective functions (e.g., VLSI placement with linear wirelength). Smoothness and convexity of the objective functions typically enable efficient minimization. If either characteristic is not present in the objective function, one can modify and/or restrict the objective to special values of parameters to provide the missing properties. After the minimizers of the modified function are found, they can be further improved with respect to the original function by fast local search using only function evaluations. Thus, it is the modification step that deserves most attention. In this paper, we approximate convex nonsmooth continuous functions by convex differentiable functions which are parameterized by a scalar fi ? 0 and have convenient limit behavior as fi ! 0. This allows the use ...
Graph theoretical problems in next generation chip design
, 2003
"... A major component of computer chip design is creating an optimal physical layout of a netlist, i.e., determining where to place the functional elements and how to route the wires connecting them when manufacturing a chip. Because of its basic structure, the overall problem of netlist layout contains ..."
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Cited by 2 (1 self)
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A major component of computer chip design is creating an optimal physical layout of a netlist, i.e., determining where to place the functional elements and how to route the wires connecting them when manufacturing a chip. Because of its basic structure, the overall problem of netlist layout contains many questions that lend themselves to graph theoretical modeling and analysis. We will describe the basic principles of netlist layout and present several graph theoretical questions inherent in the problem. Possible approaches to these questions include concepts from hypergraphs, graph partitioning, graph drawing, graph and geometric thickness, tree width, grid graphs, planar embeddings, and geometric graph theory.
Energy/area/delay Tradeoffs in the Physical Design of Onchip Segmented Bus Architecture
"... Abstract — The increasing gap between design productivity and chip complexity and the emerging SystemsOnChip (SOC) architectural template have led to the wide utilization of reusable hard Intellectual Property (IP) cores. Macro blockbased physical design implementation needs to find a well balanc ..."
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Abstract — The increasing gap between design productivity and chip complexity and the emerging SystemsOnChip (SOC) architectural template have led to the wide utilization of reusable hard Intellectual Property (IP) cores. Macro blockbased physical design implementation needs to find a well balanced solution among chip area, onchip communication energy and critical communication path delay. We present in this paper an automated way to implement an energy optimal netlist interconnecting the hard macro blocks using a heavily segmented communication architecture. We explore the entire tradeoff curve among the network energy, chip area and critical communication path delay at the floorplanning stage based on two reallife application drivers. Large energy gains with small area overheads are illustrated during the floorplanning stage. This tradeoff profile is a good guideline for the SOC designers to choose the optimal solution for their specific systems. Index Terms — Segmented bus, macro blocks, tradeoffs, floorplanning. I.
Towards Integration of Quadratic Placement and Pin Assignment
, 2005
"... ‘‘Great ability develops and reveals itself increasingly with every new assignment.” ..."
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‘‘Great ability develops and reveals itself increasingly with every new assignment.”
Force Directed Graph Drawing Algorithms for Macro Cell Placement
"... Abstract — Macro cells are used more and more in current designs as they provide the benefit of reusability directly resulting in the decrease of design cost and time. However, there lies a gap in the EDA industry for Macro cell placement tools. This paper would like to introduce the idea of using g ..."
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Abstract — Macro cells are used more and more in current designs as they provide the benefit of reusability directly resulting in the decrease of design cost and time. However, there lies a gap in the EDA industry for Macro cell placement tools. This paper would like to introduce the idea of using graphdrawing algorithms as the basis for a Macro cell placement tool in order to obtain successful layouts. Index Terms — design automation, Macro cell, placement tool, force directed algorithm, graph drawing
Graph Drawing for Floorplanning with Flexible Blocks
"... We discuss further development of a modified forcedirected graph drawing placement algorithm for reducing wire length while placing flexible blocks during the floorplanning stage of computer chip design. An effective repelling perimeter allows floorplanning blocks and to pass through each other dur ..."
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We discuss further development of a modified forcedirected graph drawing placement algorithm for reducing wire length while placing flexible blocks during the floorplanning stage of computer chip design. An effective repelling perimeter allows floorplanning blocks and to pass through each other during early stages of a run in response to spring tensions on the edges, yet repel just enough to avoid overlap in later stages. Pressure equalization equations permit flexible blocks to reshape dynamically in reaction to penetration from neighboring blocks. We present a number of experimental results demonstrating the feasibility of this approach, achieving up to 31 % wirelength improvement over commercial tools.