We present Pegasus, a compact and expressive intermediate representation for imperative languages. The representation is suitable for target architectures supporting predicated execution and aggressive speculation. In Pegasus information about the global dataflow of the program is encoded in local structures, enabling compact and efficient algorithms for program optimizations. As a proof of the versatility of Pegasus, we have used it in a compiler translating C programs to hardware implementations. 1

Approved by Dissertation Committee: This thesis is dedicated to: the gift of music pizza Beef Wellington the wines of Bordeaux mi amore

This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is always guaranteed. Moreover, a set of transformations is presented for the subclass of Free-Choice Petri nets that enables the exploration of different solutions. The set of transformations is derived from previous work on Petri net synthesis. Both the encoding technique and the set of transformations preserve the property of free-choiceness, thus enabling the use of structural methods for the synthesis of asynchronous circuits. Preliminary experimental This work has been partially funded by the Ministry of Science and Technology of Spain under contract TIC 2001-2476, ACiD-WG (IST-1999-29119), a grant by Intel Corporation and CIRIT 2001SGR-00254. results indicate that the quality of the circuits is comparable to that obtained by methods that require an exhaustive enumeration of the state space. This novel synthesis method opens the door to the synthesis of large control specifications generated from hardware description languages. Keywords: Asynchronous circuits, structural synthesis, Complete State Coding, Petri nets. 1.

A new technique for the logic synthesis of asynchronous circuits is presented. It is based on the structural theory of Petri nets and integer linear programming. The technique is capable of checking implementability conditions, such as, complete state coding, and deriving a gate netlist to implement the specified behavior. This technique can synthesize specifications with few thousands of transitions in the Petri net, providing a speed-up of several orders of magnitude with regard to other existing techniques.

None of the available minimizers for two-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and automated circuit partitioning techniques. This paper

Abstract. A known method to compute on an asynchronously updating cellular automaton is the simulation of a synchronous computing model on it. Such a scheme requires not only an increased number of cell states, but also the simulation of a global synchronization mechanism. Asynchronous systems tend to use synchronization only on a local scale—if they use it at all. Research on cellular automata that are truly asynchronous has been limited mostly to trivial phenomena, leaving issues such as computation unexplored. This paper presents an asynchronously updating cellular automaton that conducts computation without relying on a simulated global synchronization mechanism. The 2-dimensional cellular automaton employs a Moore-neighborhood and 85 totalistic transition rules describing the asynchronous interactions between the cells. Despite the probabilistic nature of asynchronous updating, the outcome of the dynamics is deterministic. This is achieved by simulating delay insensitive circuits on it, a type of asynchronous circuit that is known for its robustness to variations in the timing of signals. We implement three primitive operators on the cellular automaton from which any arbitrary delay insensitive circuit can be constructed, and show how to connect the operators such that collisions of crossing signals are avoided.

. Asynchronous circuits is a discipline in which the theory of concurrency is applied to hardware design. This paper presents an overview of a design framework in which Petri nets are used as the main behavioral model for specification. Techniques for synthesis, analysis and formal verification of asynchronous circuits are reviewed and discussed. 1 Introduction Finite State Machines has been the most traditional model of computation for sequential circuits [25, 26]. It is a state-based model in which the system, being in a state, reads some inputs, writes some outputs and moves to another state. Time is discretized by the notion of cycle, which is the time that takes the system to move from one state to another. This model is appropriate to derive circuit implementations with a periodic signal, the clock, that dictates the time instants in which the system changes state. The cycle is the finest degree of granularity at which operations are scheduled. Thus, two operations are conc...

Abstract — Delay-Insensitive (DI) circuits are a class of asynchronous circuits, whose correctness of operation is robust to arbitrary delays in modules or interconnection lines. Keller clarified the precise operating conditions of the class of DIcircuits, and presented a universal set of primitive modules from which any circuit in the class is realizable. Later, Patra presented an alternative universal set of primitive modules, and claimed that there is no universal set of primitives satisfying Keller’s conditions, in which the largest number of input and output lines of each primitive module is less than five. In this paper, we present new types of primitive modules, each having at most three input- and output-lines. and show they form a universal set of primitives. We achieve this reduction in complexity by allowing the input- and output-lines of modules to be bi-directional and to be able to buffer signals. The use of buffers in interconnection lines allows higher throughput of signals and results in circuits requiring less feedback lines, thus improving the efficiency of DI-circuits. The proposed class of DI-circuits is especially useful for implementations on cellular automata—an architecture that promises efficient implementations and manufacturing in nanotechnology due to its regular structure. Index Terms — asynchronous systems, delay-insensitive circuits, module, universality, bi-directional buffering lines I.

This paper presents “surfing, ” a novel variation of wave pipelining. In previous wave pipelined designs, timing uncertainty grows monotonically as data propagates through gates and other logic elements. Our designs propagate a timing pulse along with the data values, and our logic elements have delays that decrease in the presence of the pulse. This produces a “surfing ” effect wherein events are bound in close proximity to the timing pulse. This produces a robust variant of wave-pipelining where timing dispersion is bounded regardless of the length of the pipeline. We demonstrate our approach with the design of a simple proof-of-concept chip. 1

As embryonic arrays take inspiration from nature they display biological properties, namely complex structure and fault-tolerance. However, they have yet to take advantage of a further biological feature at a fundamental level; asynchronous operation. In addition to the benefits normally associated with asynchronous digital design, such as intrinsic power management, two areas in which embryonic arrays could benefit are scalability and reliability. This paper gives an overview of embryonic systems and a pertinent asynchronous methodology, that of macromodules. It is shown that a macromodule approach allows the implementation of asynchronous circuits on Xilinx Virtex FPGAs using only the standard design tools. A preliminary VHDL simulation illustrates the operation of an asynchronous embryonic array. Although mentioned, little detail of the reconfiguration scheme is given for brevity. This simulation brings truly asynchronous embryonic circuits a step closer.