In this paper, we present a methodology to synthesize CMOS RF devices from high-level circuit specifications into transistor netlists. The core of the methodology is an estimator of RF analog CMOS circuits, which evaluates the performance parameters of various circuit topologies. The estimation engine is based on a hierarchical analog performance estimator and a set of heuristics. The synthesis environment considers all performance parameters into account, and it relies on a genetic algorithm based heuristic method to search for a solution in a large design-space. The synthesis tool determines a solution set of design parameters such that the RF circuit satisfies the overall design constraints. 1.

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology. Global Design of Analog Cells using Statistical Optimization Techniques 3 Global Desig...

This paper introduces a complete methodology for retargeting of transistor-level circuits to different sets of specifications. By careful integration of the device sizing and layout generation tasks, fully functional designs are generated in a few minutes of CPU time. The methodology is illustrated via the retargeting of a fully-differential Miller-compensated two-stage operational amplifier for a new set of specifications. 1.