Analog Viterbi decoders are finding widespread use in class-IV partial-response disk-drive applications. These analog realizations are often used because they are smaller and consume less power than their digital counterparts. However, class-IV signaling allows simplifications during Viterbi detection and thus existing analog decoders have limited applications. The purpose of this paper is to develop efficient analog circuits that can be used for general Viterbi detection. To demonstrate the feasibility of the proposed approach, the analog portions of two analog Viterbi decoders were fabricated in a 0.8-m BiCMOS process. With an off-chip digital path memory, operation up to 50 Mb/s is demonstrated. However, simulations indicate that with on-chip digital path memory, speeds on the order of 300 Mb/s can be achieved. The power consumption of the proposed approach is estimated to be 15 mW/state drawn from a single 5-V power supply. Index Terms---Analog, BiCMOS, communications, Viterbi. I...

Analog Viterbi decoders have recently been shown to be viable alternatives to their digital counterparts. In fact, a commercial analog class-IV partial-response sequence detector for magnetic read channels has already been reported. Analog decoders offer the advantages of reduced power and size primarily due to the elimination of the A/D. The analog Viterbi decoder described here is less complex and more robust compared to other reported realizations. The decoder is based on a new derivation of the difference-metric algorithm which is developed from an analog implementation perspective. This has resulted in a decrease in hardware complexity thereby making an analog approach more attractive for today's demanding high-speed, low-power, and small-size applications, such as magnetic diskdrive storage systems. The decoder was fabricated in a 0.8-m BiCMOS process. It consists of two time-interleaved dicodes and the interleaving circuitry. The decoder was tested at up to 100 MS/s. However, si...

An area receiving significant attention both from academia and industry is data communications. Great effort is being placed at pushing data transmission rates over copper to near the Shannon limit which requires support electronics such as filters operating in the VHF range. Thus, tuning mechanisms are essential to accommodate fabrication and channel variations. One technology to accommodate these variations is that of analog adaptive filtering and is the main topic of this thesis. Specifically, this thesis is an investigation to determine and demonstrate the capability of analog adaptive filtering in practical high-speed applications. The issues that are addressed are the implementation of the tuning algorithm, simple and effective building blocks and the effects of DC offset. Herein, a curve fitting approach is proposed for the adaptation algorithm and focus is placed on simple algorithms and simple filter building blocks that can accommodate a wide tuning range and high speed. Experimental results of a 100Mb/s transmit pulse-shaping filter verify the proposed adaptive techniques and highlight practical problems. This prototype is the first demonstration of an analog adaptive filter operating in the VHF range. Attaining a