Providing efficient device driver support in the Fluke operating system presents novel challenges, which stem from two conflicting factors: (i) a design and maintenance requirement to reuse unmodified legacy device drivers, and (ii) the mismatch between the Fluke kernel's internal execution environment and the execution environment expected by these legacy device drivers. This thesis presents a solution to this conflict: a framework whose design is based on running device drivers as usermode servers, which resolves the fundamental execution environment mismatch. This approach

The Reconfigurable and Adaptive Computing Environment, or RACE, is a reconfigurable computer that has been developed in the Design Automation Laboratory at the University of Cincinnati. RACE was developed to facilitate any type of reconfigurable computing. Reconfigurable computing can be thought of as having the ability to repeatedly perform applications on a reconfigurable hardware system. Such reconfigurable hardware has been made possible by the advent of FPGAs, or Field-Programmable Gate Arrays. The RACE system has five Xilinx XC4013 FPGAs, one of which acts as a controller, which provide approximately 52,000 logic gates for computing. Furthermore, each FPGA has 128KB of local data memory and 64KB of local configuration memory, which is used to store FPGA configurations. RACE was designed to make reconfigurable computing easy to use so a library of software functions have been developed to control the reconfigurable hardware without detailed hardware knowledge of RACE. Likewise, im...

Custom computing machines based on FPGA devices have attracted much attention as a new approach toward high-performance computing. By combining state-of-the-art FPGA technology and state-of-the-art MCM packaging technology, a "configurable system" with a gate capacity of several millions of gates contained in a desk-top size box will become a reality in the near future. Developing applications for such a large configurable system is a grand challenge. FPGAs are inherently resource limited devices in terms of logic, routing, and IO. Without a careful circuit implementation strategy, one would waste a large portion of the potential capacity of the configurable hardware. Also, high-level design entry support is essential for such large-scale hardware. A C++ design tool has been implemented which maps the computational algorithms onto bit-serial pipeline networks which exhibit high performance and maximize the device utilization of each FPGA. With this tool, the designer is able to develo...