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A design methodology for highly-integrated low-power receivers for wireless communications (2001)

by D G-W Yee
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A Low-Energy Chip-Set for Wireless Intercom

by M. Josie Ammer , Michael Sheets, Tufan Karalar, Mika Kuulusa, Jan Rabaey , 2003
"... A low power wireless intercom system is designed and implemented. Two fully-operational ASICs, integrating custom and commercial IP, implement the entire digital portion of the protocol stack. Combined, the chips consume 13 mW on average when three nodes are connected to the network. A high-level de ..."
Abstract - Cited by 7 (3 self) - Add to MetaCart
A low power wireless intercom system is designed and implemented. Two fully-operational ASICs, integrating custom and commercial IP, implement the entire digital portion of the protocol stack. Combined, the chips consume 13 mW on average when three nodes are connected to the network. A high-level design methodology was used to define the protocol stack and communication algorithms, select architectures, and minimize energy.

Low Power Synchronization for Wireless Communication

by Marcy Josephine Ammer, Marcy Josephine Ammer, Marcy Josephine Ammer , 2004
"... ..."
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Algorithm/Architecture Co-Design for Wireless Communication Systems

by Ning Zhang, Ning Zhang, Ning Zhang , 2001
"... ..."
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Contents

by Peimin Chi, Second Reader
"... ii ..."
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List of Tables vi

by Richard Lu, Professor Ali, M. Niknejad, Second Reader
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An LNA and Mixer for a Global Positioning System receiver in 0.18um CMOS

by Jia-yi Chen, Tony Lin, Paul M. Walsh
"... Abstract – A CMOS low-noise amplifier (LNA) and mixer for a GPS front end is described. At 1.586Ghz the LNA minimum noise figure (NF) is 2.8dB, input third order intercept point (IIP3) is 2.45dB and forward gain is 30dB. With a 1.573Ghz local oscillator (LO) and a 1.586Ghz RF input the mixer minimum ..."
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Abstract – A CMOS low-noise amplifier (LNA) and mixer for a GPS front end is described. At 1.586Ghz the LNA minimum noise figure (NF) is 2.8dB, input third order intercept point (IIP3) is 2.45dB and forward gain is 30dB. With a 1.573Ghz local oscillator (LO) and a 1.586Ghz RF input the mixer minimum NF is 6.1dB, IIP3 is 12dB and a conversion gain of-3dB. The LNA and mixer consume 58mW of power from a 1.8V supply. The active area of the LNA and mixer is 0.5mm X 0.4mm X 0.2 mm. The prototypes are to be fabricated in a 0.18-Pm CMOS process.

Simulation and Analysis of a Low-Power . . .

by Ulrich Georg Schuster , 2002
"... Wireless sensor node networks have the potential to become the next great driver application in the further development of wireless communication systems. Ubiquitous sensor nodes of small size, low cost and low power consumption form the enabling technology behind these future sensor networks. To ..."
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Wireless sensor node networks have the potential to become the next great driver application in the further development of wireless communication systems. Ubiquitous sensor nodes of small size, low cost and low power consumption form the enabling technology behind these future sensor networks. To achieve battery–independent operation through energy scavenging, all components of the system have to be optimized for ultra–low power consumption. This is especially critical for the analog components in the radio subsystem as traditional radios account for a large part of the overall energy budget of a wireless appliance. To asses the performance of a radio link proposed by the PicoRadio RF group at the Berkeley Wireless Research Center, a simulation framework is needed that captures the behavior of the different analog building blocks. This simulation framework is described in detail; the various behavioral models of the analog components are derived and transformed into a baseband equivalent representation ready for simulation. Results of simulation runs are discussed and based on the simulation resutls, a simplified analytical model is developped, which can be used to study the effect of channel fading.
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