Advancing technology drives design technology and thus design automation (EDA). How to model interconnect, how to handle degradation of signal integrity and increasing power density are changing now, and have led to integrating logic and layout synthesis. Agressive gate sizing to control timing has become part of any modern back-end. From 0:13 and down, chips will be more susceptive to breakdown during fabrication (antenna e ect) or towear out over time (electromigration) and dealing with these issues will require careful planning. More integration of fast and accurate analysis with a complete design ow (chip planning, synthesis, placement and routing) will be needed, and still, advancing complexity will a ect design and veri cation. Using hundreds of millions of devices e ectively will be possible only by reusing pre-designed intellectual property (IP) e ectively and by addressing system-level issues in EDA. In the long term only more radical changes will keep us on Moore's track, changes that ultimately will have us depart from the two +-dimensional con nement and lead to multiple active layers, and changes that will a ect deeply the face of EDA altogether.

Abstract. Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are also introduced so that data can be associated with temporal assertions and provide more functionalities than previous temporal assertion checkers.