Abstract — Oversampling techniques based on sigma-delta (ΣΔ) modulation offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in a low-voltage environment. This paper examines the design and implementation of a CMOS ΣΔ modulator for digital-audio A/D conversion that operates from a single 1.8-V power supply. A cascaded modulator that maintains a large full-scale input range while avoiding signal clipping at internal nodes is introduced. The experimental modulator has been designed with fully-differential switched-capacitor integrators employing different input and output common-mode levels and boosted clock drivers in order to facilitate low voltage operation. Precise control of common-mode levels, high power supply noise rejection, and low power dissipation are obtained through the use of two-stage, class A/AB operational amplifiers. At a sampling rate of 4 MHz and an oversampling ratio of 80, an implementation of the modulator in a 0.8-μm CMOS technology with metal-to-polycide capacitors and NMOS and PMOS threshold voltages of +0.65-V and –0.75-V, respectively, achieves a dynamic range of 99 dB at a Nyquist conversion rate of 50 kHz. The modulator can operate from supply voltages ranging from 1.5 V to 2.5 V, occupies an active area of 1.5 mm 2, and dissipates 2.5 mW from a 1.8-V supply.

OF THE DISSERTATION An 8-Bit 150-MHz CMOS A/D Converter by Yun-Ti Wang Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 1999 Professor Behzad Razavi, Chair High-speed analog-to-digital converters (ADCs) with resolutions of 8 bits find wide application in instrumentation and communication systems. For example, portable digital oscilloscopes use 8-bit ADCs with sampling rates above one hundred megahertz. Also, the Gigabit Ethernet standard with CAT-5 copper cable requires four 125-MHz ADCs having a resolution of 7 to 8 bits to perform the frontend analog-to-digital data conversion. This dissertation presents an 8-bit, 5-stage interleaved and pipelined ADC that performs analog processing only by means of open-loop circuits such as differential pairs and source followers, thereby achieving a high conversion rate. The concept of "sliding interpolation" is proposed to obviate the need for a large number of comparators or interstage digital-to-analog conve...

The power dissipation of an analog-to-digital converter (ADC) is a function of many variables, such as sampling rate (f S), resolution, architecture, process, voltage supply and technology. This chapter will attempt to establish the power dependence on sampling rate and resolution as its primary goal. To make this tenable, the scope of this task will be nar-rowed in the following two ways: 1. Architectures: Only those ADC’s suitable for use in high-speed signal processing applications, i.e., capable of attaining high Nyquist sampling rates, such as Flash, Two-step, Subranging, Folding, Interpolating and Pipelined architectures will be considered. 2. Process: Coverage will be restricted to high-integration capable IC processes such as bipolar, BiCMOS and CMOS processes which allow embedding of the ADC function in a monolithic signal processing chip. Even with a narrower scope, only a first-order analysis is attempted in light of the many variables that influence the power of an ADC. After developing power relationships for the above A/D architectures, the results of this analysis will be used to estimate the power 1 High-Speed ADC Architectures 2 variation in three high-speed system examples. 2.1 High-Speed ADC Architectures Before describing each architecture type, data gathered from published research of these types of ADC’s is presented for reference. In Fig.2-1, the resolution of the ADC’s is