OF THE DISSERTATION An 8-Bit 150-MHz CMOS A/D Converter by Yun-Ti Wang Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 1999 Professor Behzad Razavi, Chair High-speed analog-to-digital converters (ADCs) with resolutions of 8 bits find wide application in instrumentation and communication systems. For example, portable digital oscilloscopes use 8-bit ADCs with sampling rates above one hundred megahertz. Also, the Gigabit Ethernet standard with CAT-5 copper cable requires four 125-MHz ADCs having a resolution of 7 to 8 bits to perform the frontend analog-to-digital data conversion. This dissertation presents an 8-bit, 5-stage interleaved and pipelined ADC that performs analog processing only by means of open-loop circuits such as differential pairs and source followers, thereby achieving a high conversion rate. The concept of "sliding interpolation" is proposed to obviate the need for a large number of comparators or interstage digital-to-analog conve...

the degree of Doctor of Philosophy. Advances in integrated circuit technologies permit faster clocking speed and increased logic density in chips. However, advances in chip packaging technologies have not kept pace; hence the number of input/output pins and input/output bandwidth per chip has increased less rapidly. The resulting disparity creates the need for more bandwidth per pin. Single-ended signalling and simultaneous bidirectional signalling methods may each increase the bandwidth per pin by a factor of two. However, using these signalling methods poses challenges in compensating for additional noise sources and reduced noise rejection ratios. This work presents the architecture, circuit techniques, and test results for a single-ended simultaneously bidirectional interface capable of a total throughput of 8 Gigabits per second per pin. The interface addresses the noise reduction challenges by utilizing a pseudo-differential reference with noise immunity approaching that of a fully differential reference. Furthermore, noise generation is reduced by on-chip termination, and low-skew near-end outgoing signal echo cancellation. A test chip in a 0.35 micron digital CMOS technology uses these techniques for an eight bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gigabit per second per pin.