OF THE DISSERTATION An 8-Bit 150-MHz CMOS A/D Converter by Yun-Ti Wang Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 1999 Professor Behzad Razavi, Chair High-speed analog-to-digital converters (ADCs) with resolutions of 8 bits find wide application in instrumentation and communication systems. For example, portable digital oscilloscopes use 8-bit ADCs with sampling rates above one hundred megahertz. Also, the Gigabit Ethernet standard with CAT-5 copper cable requires four 125-MHz ADCs having a resolution of 7 to 8 bits to perform the frontend analog-to-digital data conversion. This dissertation presents an 8-bit, 5-stage interleaved and pipelined ADC that performs analog processing only by means of open-loop circuits such as differential pairs and source followers, thereby achieving a high conversion rate. The concept of "sliding interpolation" is proposed to obviate the need for a large number of comparators or interstage digital-to-analog conve...

A sample-and-hold amplifier designed for the front end of high-speed low-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz while allowing input/output voltage swings of 1.5 V with a 3-V supply. The circuit also incorporates a cancellation technique to relax the trade-off between the holdmode feedthrough and the sampling speed. Fabricated in a 20-GHz 1-m BiCMOS technology, an experimental prototype exhibits a harmonic distortion of 065 dB with a 10-MHz analog input and occupies an area of 220 2150 m 2 : The measured feedthrough is 052 dB for a 50-MHz analog input and the droop rate is 40 V/ns. I. INTRODUCTION T HE DESIGN of low-voltage analog and mixed-signal circuits often imposes severe speed and precision limitations upon signal processing systems. In multistep analog-to-digital (A/D) converters, for example, the front-end sample-and-hold amplifier (SHA) must achieve high speed and high linearity...