This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a grad...

INTRODUCTION Networks of resistors have been identified as interesting devices for analog computation. Since the analytical model of a network of constant resistors is a set of linear equations, such a circuit can be used to solve a large number of linear equations concurrently. Whenever such a resistive embodiment of a computational problem can be found, the resulting circuit is usually very simple, fast and dense compared to CPU-based hardware. Particular problems solved by such networks include simulation of electromagnetic fields [1], linear image filtering [2], regularization for image processing [3], and D/A conversion [4]. Networks of resistors are especially attractive for CMOS integrated circuits, since it has been shown that a circuit obtained by replacing every resistor by a single MOS transistor has exactly the same branch currents as its resistive counterpart [5]. In the following, a resistive network combining constant and controlled resistors is described, as we

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