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Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic
 Formal Methods in System Design
, 1999
"... Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the s ..."
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Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the secondorder nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way. We present a natural Kripkestyle semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic [15], in which validity is validity up to stabilisation, and implication oe comes out as "boundedly gives rise to." We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers...
Verification of VLSI Circuits: Signal Value Modeling and HDL Translation
"... . The ever increasingly number of transistors possible in VLSI circuits compounds the difficulty in ensuring correct designs. Formal verification has been touted as a means of overcoming this problem, but most of the work in this area has been directed at standalone theorem provers. Before verificat ..."
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. The ever increasingly number of transistors possible in VLSI circuits compounds the difficulty in ensuring correct designs. Formal verification has been touted as a means of overcoming this problem, but most of the work in this area has been directed at standalone theorem provers. Before verification is accepted by the VLSI design community, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by designers. The primary obstacle is that the hardware description languages (HDL's) used in verification tools are often not syntactically or semantically compatible with the hardware description languages commonly used in the VLSI design community. The research presented in this paper is directed at this problem. We have built a parser for the BOLT hardware description language in the HOL theorem proving system. This provides a means of using the same language in the theorem proving system and the VLSI CAD tools used in our ...
Network Algebra for Synchronous and Asynchronous Dataflow
"... Network algebra (NA) is proposed as a uniform algebraic framework for the description (and analysis) of dataflow networks. The core of this algebraic setting is provided by an equational theory called Basic Network Algebra (BNA). It constitutes a selection of primitives and identities from the algeb ..."
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Network algebra (NA) is proposed as a uniform algebraic framework for the description (and analysis) of dataflow networks. The core of this algebraic setting is provided by an equational theory called Basic Network Algebra (BNA). It constitutes a selection of primitives and identities from the algebra of flownomials due to [Ste86] and [CaS88&89]. Both synchronous and asynchronous dataflow networks are then investigated from the viewpoint of network algebra. To this end the NA primitives are defined such that the identities of BNA hold. These axioms are particularly strict about the role of the connections, which will be called flows of data. We describe three interpretations of the connections that satisfy the BNA identities: minimal stream delayers, stream delayers and stream retimers. Each of the above possibilities leads to a class of dataflow networks: synchronous dataflow networks, asynchronous dataflow networks and fully asynchronous dataflow networks, respectively. For each case...