A systematic general rounding procedure is proposed for floating-point arithmetic operations. This procedure consists of 2 steps: constructing a rounding table and selecting a prediction scheme. Optimization guidelines are given in each step to allow hardware to be minimized. This procedure-based rounding method has the additional advantage that verification and generalization are straightforward. Constructing a rounding table involves examining the range of the result and the shifting possibilities during the normalization step in an operation while selecting a prediction scheme depends on detail of the hardware model used. Two rounding hardware models are described. The first is shown to be identical to that reported by Santoro et al. [1]. The second is more powerful, providing solutions where the first fails. Applying this approach to the IEEE rounding modes for high-speed conventional binary multipliers reveals that round to infinity is more difficult to implement than the round to...

This paper presents a fast and accurate algorithm for printing floating-point numbers in both free- and fixed-format modes. In free-format mode, the algorithm generates the shortest, correctly rounded output string that converts to the same number when read back in, accommodating whatever rounding mode the reader uses. In fixed-format mode, the algorithm generates a correctly rounded output string using special # marks to denote insignificant trailing digits. For both modes, the algorithm employs a fast estimator to scale floating-point numbers efficiently. Keywords: floating-point printing, run-time systems 1 Introduction In this paper we present an efficient floating-point printing algorithm, which solves the output problem of converting floating-point numbers from an input base (usually a power of two) to an output base (usually ten). The algorithm supports two types of output, free format and fixed format. For free-format output the goal is to produce the shortest, correctly ro...

We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.

Floating-point (FP) numbers are used in general-purpose scientific computation and increasingly in digital signal processing and graphics as well. The manipulation of these numbers, however, is more complex and has much higher latencies than their integer counterparts. This research attempts to reduce the latencies of the commonly used FP operations: add, multiply, divide, and square root. The latency of an FADD can be improved by an estimated 20% at no extra hardware expense. By a detailed analysis of the existing two-path implementation, this work shows that the rounding step in both paths can be combined with the mantissa addition step, saving both hardware and time. The algorithm has been demonstrated through extensive computer simulation and silicon implementation. The test chip implemented in a standard 1um CMOS technology has a simulated nominal delay of 17ns. Like existing adders, the implemented adder uses a leading one prediction (LOP) circuit. This work examines LOP in a ge...

Abstract—We propose algorithms and provide some related results that make it possible to implement decimal floatingpoint arithmetic on a processor that does not have decimal operators, using the available binary floating-point functions. In this preliminary study, we focus on round-to-nearest mode only. We show that several functions in decimal32 and decimal64 arithmetic can be implemented using binary64 and binary128 floating-point arithmetic, respectively. We discuss the decimal square root and some transcendental functions. We also consider radix conversion algorithms. Keywords-decimal floating-point arithmetic; square root; transcendental functions; radix conversion. I.