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An Industrially Effective Environment for Formal Hardware Verification
 IEEE TCAD
, 2005
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Satbased assistance in abstraction refinement for symbolic trajectory evaluation
 In Computer Aided Verification (CAV
, 2006
"... Abstract. We present a SATbased algorithm for assisting users of Symbolic Trajectory Evaluation (STE) in manual abstraction refinement. As a case study, we demonstrate the usefulness of the algorithm by showing how to refine and verify an STE specification of a CAM. 1 ..."
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Abstract. We present a SATbased algorithm for assisting users of Symbolic Trajectory Evaluation (STE) in manual abstraction refinement. As a case study, we demonstrate the usefulness of the algorithm by showing how to refine and verify an STE specification of a CAM. 1
Explaining Symbolic Trajectory Evaluation by Giving it a Faithful Semantics
 In International Computer Science Symposium in Russia (CSR), volume 3967 of LNCS
, 2006
"... Abstract. Symbolic Trajectory Evaluation (STE) is a formal verification technique for hardware. The current STE semantics is not faithful to the proving power of existing STE tools, which obscures the STE theory unnecessarily. In this paper, we present a new closure semantics for STE which does matc ..."
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Cited by 3 (3 self)
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Abstract. Symbolic Trajectory Evaluation (STE) is a formal verification technique for hardware. The current STE semantics is not faithful to the proving power of existing STE tools, which obscures the STE theory unnecessarily. In this paper, we present a new closure semantics for STE which does match the proving power of STE modelcheckers, and makes STE easier to understand. 1
3Valued Circuit SAT for STE with Automatic Refinement
"... Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3valued symbolic simulation, using 0,1 and X (”unknown”), where the X is used to abstract away values of the circuit nodes. Most STE tools are BDDbased and use a dual rail represent ..."
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Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3valued symbolic simulation, using 0,1 and X (”unknown”), where the X is used to abstract away values of the circuit nodes. Most STE tools are BDDbased and use a dual rail representation for the three possible values of circuit nodes. SATbased STE tools typically use two variables for each circuit node, to comply with the dual rail representation. In this work we present a novel 3valued Circuit SATbased algorithm for STE. The STE problem is translated into a Circuit SAT instance. A solution for this instance implies a contradiction between the circuit and the STE assertion. An unSAT instance implies either that the assertion holds, or that the model is too abstract to be verified. In case of a too abstract model, we propose a refinement automatically. We implemented our 3Valued Circuit SATbased STE algorithm and applied it successfully to several STE examples. 1