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182
A CoordinateTransformed Arnoldi Algorithm for Generating Guaranteed Stable ReducedOrder Models of RLC Circuits
, 1996
"... Since the first papers on asymptotic waveform evaluation (AWE), Padébased reducedorder models have become standard for improving coupled circuitinterconnect simulation efficiency. Such models can be accurately computed using biorthogonalization algorithms like Padé via Lanczos (PVL), but the res ..."
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Cited by 72 (14 self)
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Since the first papers on asymptotic waveform evaluation (AWE), Padébased reducedorder models have become standard for improving coupled circuitinterconnect simulation efficiency. Such models can be accurately computed using biorthogonalization algorithms like Padé via Lanczos (PVL), but the resulting Padé approximates can still be unstable even when generated from stable RLC circuits. For certain classes of RC circuits it has been shown that congruence transforms, like the Arnoldi algorithm, can generate guaranteed stable and passive reducedorder models. In this paper we present a computationally efficient modelorder reduction technique, the coordinatetransformed Arnoldi algorithm, and show that this method generates arbitrarily accurate and guaranteed stable reducedorder models for RLC circuits. Examples are presented which demonstrates the enhanced stability and efficiency of the new method.
Efficient ReducedOrder Modeling of FrequencyDependent Coupling Inductances associated with 3D Interconnect Structures
, 1994
"... Reducedorder modeling techniques are now commonly used to efficiently simulate circuits combined with interconnect, but generating reducedorder models from realistic 3D structures has received less attention. In this paper we describe a Krylovsubspace based method for deriving reducedorder mode ..."
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Cited by 64 (12 self)
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Reducedorder modeling techniques are now commonly used to efficiently simulate circuits combined with interconnect, but generating reducedorder models from realistic 3D structures has received less attention. In this paper we describe a Krylovsubspace based method for deriving reducedorder models directly from the 3D magnetoquasistatic analysis program FastHenry. This new approach is no more expensive than computing an impedance matrix at a single frequency.
How to efficiently capture onchip inductance effects: introducing a new circuit element K
 In Proc. Int. Conf. on Computer Aided Design
, 2000
"... Onchip inductance extraction and analysis is becoming increasing critical. Inductance extraction can be difficult, cumbersome and impractical on large designs as inductance depends on the current return path — which is typically unknown prior to extracting and simulating the circuit model. In th ..."
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Cited by 52 (1 self)
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Onchip inductance extraction and analysis is becoming increasing critical. Inductance extraction can be difficult, cumbersome and impractical on large designs as inductance depends on the current return path — which is typically unknown prior to extracting and simulating the circuit model. In this paper, we propose a new circuit element, K, to model inductance effects, at the same time being easier to extract and analyze. K is defined as inverse of partial inductance matrix L, and has locality and sparsity normally associated with a capacitance matrix. We propose to capture inductance effects by directly extracting and simulating K, instead of partial inductance, leading to much more efficient procedure which is amenable to full chip extraction. This proposed approach has been verified through several simulation results. 1
Guaranteed Passive Balancing Transformations for Model Order Reduction
, 2002
"... The major concerns in stateoftheart model reduction algorithms are: achieving accurate models of sufficiently small size, numerically stable and efficient generation of the models, and preservation of system properties such as passivity. Algorithms such as PRIMA generate guaranteedpassive models ..."
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Cited by 46 (6 self)
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The major concerns in stateoftheart model reduction algorithms are: achieving accurate models of sufficiently small size, numerically stable and efficient generation of the models, and preservation of system properties such as passivity. Algorithms such as PRIMA generate guaranteedpassive models, for systems with special internal structure, using numerically stable and efficient Krylovsubspace iterations. Truncated Balanced Realization (TBR) algorithms, as used to date in the design automation community, can achieve smaller models with better error control, but do not necessarily preserve passivity. In this paper we show how to construct TBRlike methods that guarantee passive reduced models and in addition are applicable to statespace systems with arbitrary internal structure.
Layout Based Frequency Depended Inductance and Resistance Extraction for OnChip Interconnect Timing Analysis,” DAC
, 1998
"... Abstract—It is well understood that frequency independent lumpedelement circuits can be used to accurately model proximity and skin effects in transmission lines [7]. Furthermore, it is also understood that these circuits can be synthesized knowing only the high and the low frequency resistances an ..."
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Cited by 39 (1 self)
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Abstract—It is well understood that frequency independent lumpedelement circuits can be used to accurately model proximity and skin effects in transmission lines [7]. Furthermore, it is also understood that these circuits can be synthesized knowing only the high and the low frequency resistances and inductances [4]. Existing VLSI extraction tools however, are not efficient enough to solve for the frequency dependent resistances and inductances on large VLSI layouts, nor do they synthesize circuits suitable for timing analysis. We propose a rulesbased method that efficiently and accurately captures the high and low frequency characteristics directly from layout shapes, and subsequently synthesizes a simple frequency independent ladder circuit suitable for timing analysis. We compare our results to other simulation results. 1
Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization
 in Proc. Int. Symp. on Physical Design
"... In this paper, we first show that existing net ordering formulations to minimize noise are no longer valid with presence of inductive noise, and shield insertion is needed to minimize inductive noise. We then formulate two simultaneous shield insertion and net ordering (SINO) problems: the optimal S ..."
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Cited by 32 (15 self)
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In this paper, we first show that existing net ordering formulations to minimize noise are no longer valid with presence of inductive noise, and shield insertion is needed to minimize inductive noise. We then formulate two simultaneous shield insertion and net ordering (SINO) problems: the optimal SINO/NF problem to find a minarea SINO solution that is free of capacitive and inductive noise, and the optimal SINO/NB problem to find a minarea SINO solution that is free of capacitive noise and is under the given inductive noise bound. We reveal that both optimal SINO problems are NPhard, and propose effective approximate algorithms for the two problems. Experiments show that our SINO/NB algorithm uses from 15% to 57% fewer shield wires when compared to separated net ordering and shield insertion procedure. Furthermore, under practical noise bounds, the SINO/NB solutions use from 44% to 67% fewer shield wires when compared to SINO/NF solutions, and use 10% to 40% fewer shield wires when compared to the theoretical lower bound for optimal SINO/NF solutions. Additionally, all our algorithms are extremely efficient to finish all examples in few seconds. To the best of our knowledge, it is the first work that presents an indepth study on the simultaneous shield insertion and net ordering problem to minimize both capacitive and inductive noise.
Generating sparse partial inductance matrices with guaranteed stability
 In ICCAD
, 1995
"... This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding the smallest matrix terms, the proposed approach maintains accuracy at middle and high frequencies and is guaranteed to b ..."
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Cited by 32 (5 self)
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This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding the smallest matrix terms, the proposed approach maintains accuracy at middle and high frequencies and is guaranteed to be positive definite for any degree of sparsity (thereby producing stable circuit solutions). While the proposed technique is strictly based upon potential theory (i.e. the invariance of potential differences on the zero potential reference choice), the technique is, nevertheless, presented and discussed in both circuit and magnetic terms. The conventional and the proposed sparse formulation techniques are contrasted in terms of eigenvalues and circuit simulation results on practical examples. 1
ReturnLimited Inductances: A Practical Approach to OnChip Inductance Extraction
, 1999
"... Decreasing slew rates and efforts to reduce the RC delays of onchip interconnect through design and technology have resulted in the growing importance of inductance in analyzing interconnect response for timing and noise analysis. In this paper, we consider a practical approach for extracting appro ..."
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Cited by 29 (3 self)
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Decreasing slew rates and efforts to reduce the RC delays of onchip interconnect through design and technology have resulted in the growing importance of inductance in analyzing interconnect response for timing and noise analysis. In this paper, we consider a practical approach for extracting approximate inductances of onchip interconnect. This approach, which we call the method of returnlimited inductances, is based on performing the inductance modelling of signal lines and powerground lines independently and on taking advantage of the power and ground distribution of the chip to localize inductive coupling. A set of simple geometrybased matrix decomposition rules guide sparsification in these extractions. Keywords inductance, parasitic extraction, signal integrity I. Introduction W ITH technology scaling, chips consist of more interconnect wires of smaller cross sections packed closer together. As a result, RC delays have become an important performance limitation, and cap...
Layout Techniques for Minimizing OnChip Interconnect Self Inductance
 In Proc. Design Automation Conf
, 1998
"... Because magnetic e#ects haveamuch longer spatial range than electrostatic e#ects, an interconnect line with large inductance will be sensitive to distant variations in interconnect topology. This long range sensitivity makes it di#cult to balance delays in nets like clock trees, so for such nets ind ..."
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Cited by 27 (2 self)
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Because magnetic e#ects haveamuch longer spatial range than electrostatic e#ects, an interconnect line with large inductance will be sensitive to distant variations in interconnect topology. This long range sensitivity makes it di#cult to balance delays in nets like clock trees, so for such nets inductance must be minimized. In this paper we use two and threedimensional electromagnetic #eld solvers to compare dedicated ground planes to a less areaconsuming approach, interdigitating the signal line with ground lines. The surprising conclusion is that with very little area penalty,interdigitated ground lines are more e#ective at minimizing selfinductance than ground planes. 1 Introduction The potential for inductance to become a factor in the calculation of interconnect delay and signal integrity on deep submicron IC's has been forecast due to well known technology trends #1#. In high performance microprocessor design inductive e#ects have already begun to in#uence the design proces...
Algorithms in Fastimp: a fast and wideband impedance extraction program for complicated 3D geometries
 ACM/IEEE Design Automation Conference
, 2003
"... Abstract—In this paper, we describe the algorithms used in FastImp, a program for accurate analysis of wideband electromagnetic effects in very complicated geometries of conductors. The program is based on a recently developed surface integral formulation and a precorrected fast Fourier transform ( ..."
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Cited by 26 (12 self)
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Abstract—In this paper, we describe the algorithms used in FastImp, a program for accurate analysis of wideband electromagnetic effects in very complicated geometries of conductors. The program is based on a recently developed surface integral formulation and a precorrected fast Fourier transform (FFT) accelerated iterative method, but includes a new piecewise quadrature panel integration scheme, a new scaling and preconditioning technique as well as a generalized grid interpolation and projection strategy. Computational results are given on a variety of integrated circuit interconnect structures to demonstrate that FastImp is robust and can accurately analyze very complicated geometries of conductors. Index Terms—Fast integral equation solver, panel integration, parasitic extraction, preconditioner, surface integral formulation, wideband analysis. I.