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A local circuit topology for inductive parasitics
, 2002
"... A novel circuit topology for inductive coupling between interconnecting wires is presented. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for longrange coupling by propagating the vector potential from one wire to the next. E ..."
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Cited by 17 (2 self)
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A novel circuit topology for inductive coupling between interconnecting wires is presented. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for longrange coupling by propagating the vector potential from one wire to the next. Examples of model calibration, both directly from layout and as modelorder reduction of a given inductance matrix, are presented for simple wiring structures.
Efficient Inductance Extraction using CircuitAware Techniques
 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS
, 2002
"... We propose two practical approaches for onchip inductance extraction to obtain a highly sparsified and accurate inverse inductance matrix K. Both approaches differ from previous methods in that they use circuit characteristics to obtain a sparse, stable and symmetric K, using the concept of resista ..."
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Cited by 1 (1 self)
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We propose two practical approaches for onchip inductance extraction to obtain a highly sparsified and accurate inverse inductance matrix K. Both approaches differ from previous methods in that they use circuit characteristics to obtain a sparse, stable and symmetric K, using the concept of resistancedominant and inductancedominant lines. Specifically, they begin by finding inductancedominant lines and forming initial clusters, followed by heuristically enlarging and/or combining these clusters, with the goal of including only the important inductance terms in the sparsified K matrix. Algorithm 1 permits the influence of the magnetic field of aggressor lines to reach the edge of the chip, while Algorithm 2 works under the simplified assumptions that the supply lines have zero j ij dt dI L ) / ( drops (but have nonzero parasitic R's and C's), and that currents cannot return through supply lines beyond a userdefined distance. For reasonable designs, Algorithm 1 delivers a sparsification of 97% for delay and oscillation magnitude errors of 10% and 15%, respectively, as compared to Algorithm 2 where the sparsification can reach 99% for the same delay error. An offshoot of this work is the development of KPRIMA, an extension of the reducedorder modeling technique, PRIMA, to handle K matrices with guarantees of passivity.
INDUCTANCE MODELING FOR ONCHIP INTERCONNECTS
"... As the operation frequency reaches gigahertz in deepsubmicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are fieldsolvers, which are intrinsically more accurate but computationally expensive. Others focus on ..."
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Cited by 1 (0 self)
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As the operation frequency reaches gigahertz in deepsubmicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are fieldsolvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them online into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10 % for practical cases. In particular, our method is very fast. Based on our study, we also suggest several routing topologies for inductance minimization.
TABLE OF CONTENTS
"... Deliverable: D1.2a Title: D1.2a Report on compact electromagnetic modelling of RF integrated structures ..."
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Deliverable: D1.2a Title: D1.2a Report on compact electromagnetic modelling of RF integrated structures
OnChip Inductance Extraction, Simulation and Modeling
, 2002
"... This is to certify that I have examined this copy of a doctoral thesis by ..."
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This is to certify that I have examined this copy of a doctoral thesis by
HIGHLIGHTS IN PHYSICAL SIMULATION AND ANALYSIS AT ICCAD
"... Six papers were chosen to represent twenty years of research in physical simulation and analysis, three papers addressing the problem of extracting and simulating interconnect effects and three papers describing techniques for simulating steadystate and noise behavior in RF circuits. In this commen ..."
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Six papers were chosen to represent twenty years of research in physical simulation and analysis, three papers addressing the problem of extracting and simulating interconnect effects and three papers describing techniques for simulating steadystate and noise behavior in RF circuits. In this commentary paper we will try to describe the contribution of each paper and place that contribution in some historical context.