. This paper presents the PACE partitioning algorithm which is used in the LYCOS co-synthesis system for partitioning control/dataflow graphs into hardwareand software parts. The algorithm is a dynamic programming algorithm which solves both the problem of minimizing system execution time with a hardware area constraint and the problem of minimizing hardware area with a system execution time constraint. The target architecture consists of a single microprocessor and a single hardware chip (ASIC, FPGA, etc.) which are connected by a communication channel. The algorithm incorporates a realistic communication model and thus attempts to minimize communication overhead. The time-complexity of the algorithm is O(n 2 \Delta A) and the space-complexity is O(n \Delta A) where A is the total area of the hardware chip and n the number of code fragments which may be placed in either hardware or software. 1 Introduction The hardware/software partitioning of a system specification onto a target...

The objective of this paper is to introduce the Stochastic Automata Networks (SANs) as an effective formalism for application modeling in system-level analysis. More precisely, we present a methodology for application modeling for system-level power/performance analysis that can help the designer to select the right platform and implement a set of target multimedia applications. We also show that, under various input traces, the steady-state behavior of the application itself is characterized by very different ‘clusterings’ of the probability distributions. Having this information available, not only helps to avoid lengthy profiling simulations for predicting power and performance figures, but also enables efficient mappings of the applications onto a chosen platform. We illustrate the benefits of our methodology using the MPEG-2 video decoder as the driver application.

to my mother Luzia, andinmemoryofmyfatherKarl-Heinz IV Table of Contents Table of Contents

System specification and design consists of describing a system's desired functionality, and of mapping that functionality for implementation on a set of system components, such as processors, ASIC's, memories, and buses. In this article, we describe the key problems of system specification and design, including specification capture, design exploration, hierarchical modeling, software and hardware synthesis, and cosimulation. We highlight existing tools and methods for solving those problems, and we discuss issues that remain to be solved. 1 Introduction Embedded systems have become commonplace in recent years. Examples include automobile cruise-control, fuel-injection systems, aircraft autopilots, telecommunication products, interactive television processors, network switches, video focusing units, robot controllers, and numerous medical devices. While there is no widespread agreement of what defines an embedded system, we note that such systems possess a few key characteristics. Th...

This dissertation presents methods for automating the synthesis of embedded systems, i.e., special-purpose computers. In addition, it describes a method for analyzing the manner in which real-time operating system use influences embedded system power consumption.

Given a set of specifications for a targeted application, algorithm selection refers to choosing the most suitable algorithm for a given goal, among several functionally equivalent algorithms. We demonstrate an extraordinary potential of algorithm selection for achieving high throughput, low cost, and low power implementations. We introduce an efficient technique for low-bound evaluation of the throughput and cost during algorithm selection and propose a relaxation-based heuristic for throughput optimization. We also present an algorithm for cost optimization using algorithm selection. The effectiveness of methodology and algorithms is illustrated using examples. 1.0 Motivations There is a wide consensus among CAD researchers and

This paper addresses fundamental aspects of system modelling and partitioning algorithms in the area of Hardware/Software Codesign. Three basic system models for partitioning are presented and the consequences of partitioning according to each of these are analyzed. The analysis shows the importance of making a clear distinction between the model used for partitioning and the model used for evaluation. It also illustrates the importance of having a realistic hardware model such that hardware sharing can be taken into account. Finally, the importance of integrating scheduling and allocation with partitioning is demonstrated. 1 Introduction Hardware/software partitioning is often viewed as the synthesis of an architecture consisting of a single CPU and a single dedicated hardware component (full custom, FPGA, etc.) from an initial system specification, e.g., [1]. The aim of this paper is to emphasize the importance of clearly defining and reporting the partitioning model assumed by a pa...

Program profiling is common way to characterize program behavior based on representative input. Some software, especially in embedded systems, cannot be profiled do to lack of tools or problems introduced by instrumentation of the code. As an alternative to traditionally profiling, a static analysis technique is proposed that allows a designer to characterize the flow of control of software. Operating on a flow graph representation of software, the proposed technique assists an expert designer in the specification of one or more representative scenarios. A scenario defines a specific flow of control that corresponds to a typical behavior of the system. The efficacy of the technique is demonstrated with two experiments: a comparison to traditional profiling and application to real embedded operating system software for which traditional profiling is not possible.

Partitioning a system's functionality among interacting hardware and software components is an important part of system design. We introduce a new partitioning algorithm that caters to the main objective of the hardware/software partitioning problem, i.e. minimizing hardware for given performance constraints. We demonstrate results superior to those of previously published algorithms intended for hardware/software partitioning. Contents 1 Introduction 2 2 Problem Definition 4 3 Solving the hardware/software partitioning problem 5 3.1 Greedy algorithms : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 5 3.2 Hill-climbing algorithms : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 6 3.3 A new algorithm based on constraint-search : : : : : : : : : : : : : : : : : : 8 3.3.1 Foundation : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8 3.3.2 Algorithm : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 10 3.3.3 Reducing runtime in p...

Recent evolution in system-on-chip (SOC) design methodology demonstrates an important omission of a design principle that directly contributes to the success of conventional computer systems: the use of a simple programming model to separate application from architecture. In an effort to restore the powerful concept of programming in the context of system-on-chip, in this work we propose a new programming model, called context-flow, that is general-purpose, simple, safe, highly parallelizable yet transparent to the underlying architectural details. A high-performance SOC platform architecture is then designed to support this programming model, while fully exploiting the physical proximity between the processing elements. Using an architectural exploration framework with a multi-processor simulator, our case studies on real life applications demonstrate the feasibility of adapting imperative C programs to context-flow programs, as well as the performance efficiency of our context-flow architecture over bus-based and packet-switch-based alternatives. Finally, we propose an analytical performance model, based on queueing networks, for the new SOC platform architecture that is simple, synthesis-friendly, and as flexible and powerful as queueing theory.