Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics are treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. When compared to the deterministic optimization, the new algorithm, on average, reduces static power by 31 % and total power by 17 % without the loss of parametric yield. The run time on a variety of public and industrial benchmarks is 30X faster than other known statistical power minimization algorithms.

Recent years have seen an increase in the importance of on-chip wires, as they have slowed down and gates have sped up. This dissertation takes a close look at the story of wire scaling. It forecasts wire and gate characteristics from the Semiconductor Industry Association roadmap and combines them into performance metrics, showing how the ratio of wire delays to gate delays scales slowly for scaled-length wires and grows rapidly for fixed-length wires.

A 4-bit 12-GSample/sec A/D converter (GAD) has been fabricated in a 0.25-μm CMOS process to investigate the design of an equalized multi-level link. Clocked differential amplifiers were used to sample the input, followed by high-speed comparators with current-summed offset cancellation. Input bandwidth was measured at 2.5 GHz. Eight 1.5-GSample/sec flash A/D converters were interleaved to achieve the aggregate sample rate.

The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important forproducing imaging systems that can be manufactured with low cost, low power, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Pattern Noise (FPN) and Signal-to-Noise-Ratio (SNR) of the video output. This research focuses on minimizing FPN and improving SNR in linear CMOS image sensors which are needed in scanning and swiping applications such as nger print sensing, spectroscopy, and medical imaging systems. FPN is reduced in this research through the use of closed loop operational ampli ers in active pixels and through performing Correlated Double Sampling (CDS). SNR is improved by increasing the pixel saturation voltage. This thesis concludes that FPN can be reduced using the closed loop opamp bu ers. The major FPN noise sources are the shot noise from the photodiode, kTC noise from the sampling capacitors, and o set mismatches in the sample and hold ampli ers all of which are not compensated by CDS. Sample and hold ampli er o set mismatch is identi ed as

Charge-Base Capacitance Measurement (CBCM) techniques provide a simple way for measuring the overall parasitic capacitance of on-chip interconnects [1]. However, CBCM suffers from charge injection that limits its accuracy and sensitivity. In this paper we provide extensive simulation and experimental results showing that the effects of charge injection cannot be neglected, nor completely compensated by means of differential measures. To overcome this limitation we propose a modified scheme that makes use of complementary pass-gates with compensating charge injection phenomena. Both the original and the enhanced CBCM techniques have been implemented in 0.18μm and 0.13μm CMOS processes. Comparative experimental results are reported and discussed. 1.

I would like to express my heartfelt gratitude to my advisor Prof. Richard Carley, who has been a constant source of guidance and encouragement, throughout. A note of special thanks and appreciation is due to Prof. Tamal Mukherjee for agreeing to review the report at such a short notice. I am extremely grateful to him for his valuable comments. I would also like to thank all my friends at Pittsburgh for their help and support. Analog-to-digital converters (ADCs) are required to convert the real world analog signals into digital signals. As digital signals are more robust and easier to handle, signal processing is increasingly being done in the digital domain. This along with the increasing levels of integration has forced the ADCs to reside on the same chip as digital circuits. Designing ADCs in technologies best suited for digital circuits and operating from low voltage supplies is a challenging task. More so as the threshold voltage of the devices do not scale at the same rate as the power supply voltages. This implies very tight headroom constraints for analog designs. Design of a 6-bit ADC capable of operating at more than 300MS/s while operating from

The ASIC can delay 4 digital signals in the range 0-24 ns with 1 ns single step. The delay values of the four channels can be independently programmed by an I 2 C field bus interface. A delay locked loop (DLL) generates the control voltage used for controlling the four delay channels. The common control voltage guarantees independence from process, supply voltage and temperature variations. The DLL is synchronised to an external 40 MHz clock signal. A first version of the chip was developed in 0.8 µm CMOS technology. The design of the prototype has then been transferred with few modifications to DMILL radiation hard process. Design functionality and measurement results will be presented. 1.