Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics are treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. When compared to the deterministic optimization, the new algorithm, on average, reduces static power by 31 % and total power by 17 % without the loss of parametric yield. The run time on a variety of public and industrial benchmarks is 30X faster than other known statistical power minimization algorithms.

This paper explores the effectiveness of the simultaneous application of pipelining and parallel processing as a total power (static plus dynamic) reduction technique in digital systems. Previous studies have been limited to either pipelining or parallel processing, but both techniques can be used together to reduce supply voltage at a fixed throughput point. According to our first-order analyses, there exist optimal combinations of pipelining depth and parallel processing width to minimize total power consumption. We show that the leakage power from both subthreshold and gate-oxide tunneling plays a significant role in determining the optimal combination of pipelining depth and parallel processing width. Our experiments are conducted with timing information derived from a 65nm technology and fanout-of-four (FO4) inverter chains. The experiments show that the optimal combinations of both pipelining and parallel processing—8~12×FO4 logic depth pipelining with 2~3-wide parallel processing—can reduce the total power by as much as 40 % compared to an optimal system using only pipelining or parallel processing alone. We extend our study to show how process parameter variations—an increasingly important factor in nanometer technologies—affects these results. Our analyses reveal that the variations shift the optimal points to shallower pipelining and narrower parallel processing—12×FO4 logic depth with 2-wide parallel processing—at a fixed yield point. 1.

An energy optimization is proposed that addresses the nontrivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and behavioral models are used to quantify architectural tradeoffs across the analog/digital boundary. An interleaved ADC is optimized as a case study to demonstrate this approach. The chosen operating point of 36 channels and 700mV operation gives a 3 × improvement in energy compared to the seed of the model. The model matches closely the measured results of an ADC testchip implemented in a 65nm CMOS process.

Power consumption has become one of the most critical concerns for processor design. Parallelism offers a pathway to increased performance under power constraints — many slow processors can complete a parallel implementation of a task using less time and less energy than a fast uniprocessor. This relies on the energy-time trade-offs present in CMOS circuits, including voltage scaling. Understanding these trade-offs and their connection with algorithms will be a key for extracting performance in future multicore processor designs. I propose simple models for analysing algorithms and deriving lower bounds that reflect the energy-time trade-offs and parallelism of CMOS circuits. For example, the models constrain computational elements to lie in a two-dimensional topology. These elements, called processing elements (PEs), compute arbitrary functions of a constant number of input bits and store a constant-bounded memory. PEs are used to implement wires; thus subsuming and accounting for communication costs. Each operation of a PE takes time t and consumes energy e, where et α remains invariant for some fixed α> 0. Not only may different PEs independently trade time for energy in this way, but the same PE may vary the trade-off on an operation by operation basis.