Results 1  10
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12
An Efficient Algorithm for Statistical Minimization of Total Power under Timing Yield Constraints
 In DAC
, 2005
"... Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics are treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold voltage assignment ..."
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Cited by 56 (1 self)
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Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics are treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold voltage assignment. An extremely fast runtime is achieved by casting the problem as a secondorder conic problem and solving it using efficient interiorpoint optimization methods. When compared to the deterministic optimization, the new algorithm, on average, reduces static power by 31 % and total power by 17 % without the loss of parametric yield. The run time on a variety of public and industrial benchmarks is 30X faster than other known statistical power minimization algorithms.
Minimization of Dynamic and Static Power Through Joint Assignment of Threshold Voltages and Sizing Optimization
 in Proc. Int. Symp. on Low Power Electronics and Design
, 2003
"... We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous assignment of Vth with gate sizing. We propose an efficient algorithm based on linear programming that jointly performs Vt ..."
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Cited by 46 (1 self)
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We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous assignment of Vth with gate sizing. We propose an efficient algorithm based on linear programming that jointly performs Vth assignment and gate sizing to minimize total power under delay constraints. First, linear programming assigns the optimal amounts of slack to gates based on powerdelay sensitivity. Then, an optimal gate configuration, in terms of Vth and transistor sizes, is selected by an exhaustive local search. Benchmark results for the algorithm show 32 % reduction in power consumption on average, compared to sizing only power minimization. There is up to a 57 % reduction for some circuits. The flow can be extended to dual supply voltage libraries to yield further power savings.
Total Power Optimization by Simultaneous DualVt Allocation and Device Sizing in High Performance Microprocessors
, 2002
"... We describe various design automation solutions for design migration to a dualVt process technology. We include the results of a Lagrangian Relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dualVt allocation and sizing reduces total power by 10+% compared with Vt al ..."
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Cited by 21 (1 self)
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We describe various design automation solutions for design migration to a dualVt process technology. We include the results of a Lagrangian Relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dualVt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5x larger computation runtime than iSTATS due to its iterative nature.
Leakage Power Reduction by DualVth Designs under Probabilistic Analysis of Vth Variation
, 2004
"... Lowpower circuits are especially sensitive to the increasing levels of process variability and uncertainty. In this paper we study the problem of leakage power minimization through dual Vth design techniques in the presence of significant Vth variation. For the first time we consider the optimal se ..."
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Cited by 20 (0 self)
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Lowpower circuits are especially sensitive to the increasing levels of process variability and uncertainty. In this paper we study the problem of leakage power minimization through dual Vth design techniques in the presence of significant Vth variation. For the first time we consider the optimal selection of Vth under a statistical model of threshold variation. Probabilistic analytical models are introduced to account for the impact of Vth uncertainty on leakage power and timing slack. Using this model, we show that the nonprobabilistic analysis significantly (by 3x) underestimates the leakage power. We also show that in the presence of variability the optimal value of the second Vth must be about 30mV higher compared to the variationfree scenario. In addition, this model provides a way to compute the optimal value of the second Vth for a variety of process conditions.
Leakage minimization of nanoscale circuits in the presence of systematic and random variations
 Proc. DAC, 2005
"... This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of [18] is extended to include th ..."
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Cited by 9 (0 self)
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This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the αpercentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objective function is O(N 2) and that of evaluating the delay constraints is O(N  + E) for a circuit with N  gates and E  wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.
LOGIC SYNTHESIS FOR LOW POWER
, 2002
"... Energyefficient design of integrated circuits requires specialized tools and technologies. This chapter surveys some of the most important contributions in logic synthesis for achieving lowpower consumption, by means of gatelevel and registertransfer level restructuring. It presents also special ..."
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Energyefficient design of integrated circuits requires specialized tools and technologies. This chapter surveys some of the most important contributions in logic synthesis for achieving lowpower consumption, by means of gatelevel and registertransfer level restructuring. It presents also specialized techniques that leverage specific lowpower silicon technologies.
Post Signoff Leakage Power Optimization
"... With the scaling down of the CMOS technologies, leakage power is becoming an increasingly important issue in IC design. There is a tradeoff between subthreshold leakage power consumption and clock frequency in the circuit; i.e., for higher performance, leakage power consumption must be sacrificed a ..."
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With the scaling down of the CMOS technologies, leakage power is becoming an increasingly important issue in IC design. There is a tradeoff between subthreshold leakage power consumption and clock frequency in the circuit; i.e., for higher performance, leakage power consumption must be sacrificed and vice versa. Meanwhile, timing analysis during synthesis and physical design is pessimistic, which means there are some slacks available to be traded for leakage power minimization. This power minimization can be done after the signoff which is more accurate and realistic than if it is done before the signoff. The available slack can be traded for leakage power minimization by footprintbased cell swapping and threshold voltage assignment. In this paper, we introduce our post signoff leakage power optimization problem as a nonlinear mathematical program and solve it by using conjugate gradient (CG) method. We set up a novel transformation technique to manipulate the constraints of the optimization problem to be solved by CG. We show that by doing this optimization we can reduce the leakage power consumption by 34 % on average in comparison with no power optimization after signoff. All experiments are done on the real industrial designs.
SelfCompensating Design for Reduction of Timing and Leakage Sensitivity to Systematic PatternDependent Variation
"... Abstract—Critical dimension (CD) variation caused by defocus is largely systematic with dense lines “smiling ” through focus while isolated lines “frown. ” In this paper, we propose a new design methodology that allows explicit compensation of focusdependent CD variation, in particular, either with ..."
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Abstract—Critical dimension (CD) variation caused by defocus is largely systematic with dense lines “smiling ” through focus while isolated lines “frown. ” In this paper, we propose a new design methodology that allows explicit compensation of focusdependent CD variation, in particular, either within a cell (selfcompensated cells) or across cells in a critical path (selfcompensated design). By creating iso and dense variants for each library cell, we can achieve designs that are more robust to focus variation. Optimization with a mixture of dense and iso cell variants is possible, both for area and leakage power in timing constraints (critical delay), with the latter an interesting complement to existing leakagereduction techniques, such as dualVth. We implement both a heuristic and mixedinteger linearprogramming (MILP) solution methods to address this optimization and experimentally compare their results. Results indicate that designing with a selfcompensated
Dedication
, 2007
"... The Dissertation Committee for Ashish Kumar Singh Certifies that this is the approved version of the following dissertation: ..."
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The Dissertation Committee for Ashish Kumar Singh Certifies that this is the approved version of the following dissertation:
1.1 Leakage Power Reduction by DualVth Designs Under Probabilistic Analysis of Vth Variation
"... Lowpower circuits are especially sensitive to the increasing levels of process variability and uncertainty. In this paper we study the problem of leakage power minimization through dual Vth design techniques in the presence of significant Vth variation. For the first time we consider the optimal se ..."
Abstract
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Lowpower circuits are especially sensitive to the increasing levels of process variability and uncertainty. In this paper we study the problem of leakage power minimization through dual Vth design techniques in the presence of significant Vth variation. For the first time we consider the optimal selection of Vth under a statistical model of threshold variation. Probabilistic analytical models are introduced to account for the impact of Vth uncertainty on leakage power and timing slack. Using this model, we show that the nonprobabilistic analysis significantly (by 3x) underestimates the leakage power. We also show that in the presence of variability the optimal value of the second Vth must be about 30mV higher compared to the variationfree scenario. In addition, this model provides a way to compute the optimal value of the second Vth for a variety of process conditions.