An algorithm for unifying the techniques of gate sizing and clockskew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.

Reconfigurable arrays have been used to speed up computational tasks, some times achieving orders of magnitude of improvement either in cost/performance or raw performance. An integral part of such systems is a significant amount of memory, distributed among multiple reconfigurable chips. The current scaling trend of VLSI technology, that allows packing of more and more gates on a single silicon die, tends to throw such architectures out of balance, unless significant amount of memory is integrated on the die, close to the processing elements. Embedded DRAM technology, integration of dynamic RAM with logic circuits on the same chip, offers a unique opportunity to balance the processing and memory resources in large reconfigurable chips. In this thesis I evaluate the potential ...