Abstract—A time-interleaved A–D converter (ADC) system is an effective way to implement a high-sampling-rate ADC with relatively slow circuits. In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. However, mismatches such as offset, gain mismatches among channel ADCs as well as timing skew of the clocks distributed to them degrade S/N of the ADC system as a whole. This paper analyzes the channel mismatch effects in the time-interleaved ADC system. Previous analysis showed the effect for each mismatch individually,however in this paper we derive explicit formulas for the mismatch effects when all of offset, gain and timing mismatches exist together. We have clarified that the gain and timing mismatch effects interact with each other but the offset mismatch effect is independent from them, and this can be seen clearly in frequency domain. We also discuss the bandwidth mismatch effect. The derived formulas can be used for calibration algorithms to compensate for the channel mismatch effects. Index Terms—A–D converter, analog circuit, calibration, channel mismatch, interleave, track/hold circuit. I.

Abstract — A low-noise multibit sigma–delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-"m CMOS process, cascades a second-order 5-b sigma–delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of 098 dB with a 100-kHz input signal. Index Terms—Analog-digital conversion, bootstrapped switch, digital filters, dynamic element matching, pipeline processing, sigma–delta modulation, switched capacitor circuits. I.

Offset mismatch, gain mismatch, and sample-time error between time-interleaved channels limit the performance of time-interleaved analog-to-digital converters (ADCs). This paper focuses on the sample-time error. Techniques for correcting and detecting sample-time error in a two-channel ADC are described, and simulation results are presented.

OF THE DISSERTATION An 8-Bit 150-MHz CMOS A/D Converter by Yun-Ti Wang Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 1999 Professor Behzad Razavi, Chair High-speed analog-to-digital converters (ADCs) with resolutions of 8 bits find wide application in instrumentation and communication systems. For example, portable digital oscilloscopes use 8-bit ADCs with sampling rates above one hundred megahertz. Also, the Gigabit Ethernet standard with CAT-5 copper cable requires four 125-MHz ADCs having a resolution of 7 to 8 bits to perform the frontend analog-to-digital data conversion. This dissertation presents an 8-bit, 5-stage interleaved and pipelined ADC that performs analog processing only by means of open-loop circuits such as differential pairs and source followers, thereby achieving a high conversion rate. The concept of "sliding interpolation" is proposed to obviate the need for a large number of comparators or interstage digital-to-analog conve...

3/27/2006>REPLACE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT)< Abstract—The sample-and-hold amplifier (SHA) in each channel of a time-interleaved analog-to-digital converter system has finite bandwidth, and these bandwidths may be mismatched. This paper analyzes the effect of such mismatches. Correction for bandwidth mismatch in the digital domain is described and demonstrated. Index Terms—Analog-digital conversion, FIR digital filters, Sample and hold circuit, Bandwidth mismatch.

and Computer Sciences

The power dissipation of an analog-to-digital converter (ADC) is a function of many variables, such as sampling rate (f S), resolution, architecture, process, voltage supply and technology. This chapter will attempt to establish the power dependence on sampling rate and resolution as its primary goal. To make this tenable, the scope of this task will be nar-rowed in the following two ways: 1. Architectures: Only those ADC’s suitable for use in high-speed signal processing applications, i.e., capable of attaining high Nyquist sampling rates, such as Flash, Two-step, Subranging, Folding, Interpolating and Pipelined architectures will be considered. 2. Process: Coverage will be restricted to high-integration capable IC processes such as bipolar, BiCMOS and CMOS processes which allow embedding of the ADC function in a monolithic signal processing chip. Even with a narrower scope, only a first-order analysis is attempted in light of the many variables that influence the power of an ADC. After developing power relationships for the above A/D architectures, the results of this analysis will be used to estimate the power 1 High-Speed ADC Architectures 2 variation in three high-speed system examples. 2.1 High-Speed ADC Architectures Before describing each architecture type, data gathered from published research of these types of ADC’s is presented for reference. In Fig.2-1, the resolution of the ADC’s is

A 170-MHz analog finite impulse response (FIR) filter operating from a single 3.3-V supply is described. The design has been fabricated in the HP 1.2-m CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using multiplying digital-to-analog converters (MDAC's) with 6-b resolution. Index Terms---Analog FIR filter, circular buffer architecture, discrete-time, fixed pattern noise, low power CMOS circuits. I. INTRODUCTION M ANY applications require high-speed low-power equalizers with moderate resolution. Analog equalizers are almost ideally suited for these applications since they can typically provide the required performance with less power and area than their digital counterparts. As an example, modern magnetic storage channels, which usually use partial-response maximum-likelihood (PRML) detection, require a linear equalizer to shape the channel response [1]--[4]. Th...

We present a digital background technique for correcting the time and gain mismatches in a time-interleaved analog-to-digital converter (ADC) system. The proposed approach is applicable to any number of time-interleaved ADCs and requires only modest oversampling. While the algorithm is mainly designed for blind calibration, it can as well be operated in non-blind mode. Theoretical analysis and numerical simulations show fast convergence and good estimation performance of the proposed algorithm. For instance, for an 8-ADC system, numerical experiments demonstrate that the resulting signal to noise ratio (SNR) of the output signal after mismatch detection and interpolation, is higher than the SNR of the input signal.

iii ivZusammenfassung Moderne Signalverarbeitungsanwendungen, wie sie in der Nachrichtentechnik und Messtechnik verwendet werden, benötigen sehr schnelle Analog-Digital-Umsetzer (ADU), was durch eine räumlich parallele Anordnung von zeitlich versetzt arbeitenden ADUs (ADU-Array) erreicht werden kann. Die zeitliche Verschiebung ermöglicht, im Vergleich