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In this paper, we present a new multilevel k-way hypergraph partitioning algorithm that substantially outperforms the existing state-of-the-art K-PM=LR algorithm for multiway partitioning, both for optimizing local as well as global objectives. Experiments on

This paper addresses the problem of one-dimensional partitioning of structurally unsymmetricsquare and rectangular sparse matrices for parallel matrix-vector and matrix-transposevector multiplies. The objective is to minimize the communication cost while maintaining the balance on computational loads of processors. Most of the existing partitioning models consider only the total message volume hoping that minimizing this communication-cost metric is likely to reduce other metrics. However, the total message latency (start-up time) may be more important than the total message volume. Furthermore, the maximum message volume and latency handled by a single processor are also important metrics. We propose a two-phase approach that encapsulates all these four communication-cost metrics. The objective in the first phase is to minimize the total message volume while maintainingthe computational-load balance. The objective in the second phase is to encapsulate the remaining three communication-cost metrics. We propose communicationhypergraph and partitioning models for the second phase. We then present several methods for partitioning communication hypergraphs. Experiments on a wide range of test matrices show that the proposed approach yields very effective partitioning results. A parallel implementation on a PC cluster verifies that the theoretical improvements shown by partitioning results hold in practice.

It is known to many researchers in the partitioning community that the recursive bipartitioning approach outperforms the direct non-recursive approach in solving the multiway partitioning problem. However, little progress has been made to identify and overcome the weakness of the direct (alternatively called flat) approach. In this paper, we make the first observation that the performance of iterative improvement-based flat multiway partitioner K-FM [10, 11] is not suitable for today's large scale circuits. Then, we propose a simple yet effective hill-climbing method called PM (Pairwise cell Movement) that overcomes the limitation of K-FM and provides partitioners the capability to explore wider range of solution space effectively while ensuring convergence to satisfying suboptimal solutions. The main idea is to reduce the multiway partitioning problem to sets of concurrent bipartitioning problems. Starting with an initial multiway partition of the netlist, we apply 2-way FM [7] to pai...

Recursive bisection based placement is well known, and recent advances in partitioning have made the approach more attractive. While partitioners can optimize a placement from a local perspective, high performance design requires consideration of global issues as well. We focus on aspects of the placement problem which cannot be captured with bisection, addressing them through a new approach derived from recent work on k-way partitioning. We consider large values of k, and objective functions which are more complex than the traditional min-cut.

Decomposition of large engineering system models is desirable since increased model size reduces reliability and speed of numerical solution algorithms. The article presents a methodology for optimal model-based decomposition (OMBD) of design problems, whether or not initially cast as optimization problems. The overall model is represented by a hypergraph and is optimally partitioned into weakly connected subgraphs that satisfy decomposition constraints. Spectral graph-partitioning methods together with iterative improvement techniques are proposed for hypergraph partitioning. A known spectral K-partitioning formulation, which accounts for partition sizes and edge weights, is extended to graphs with also vertex weights. The OMBD formulation is robust enough to account for computational demands and resources and strength of interdependencies between the computational modules contained in the model. KEYWORDS: Model decomposition, multidisciplinary design, hypergraph partitioning, larges...

We illustrate how technical contributions in the VLSI CAD partitioning literature can fail to provide one or more of: (i) reproducible results and descriptions, (ii) an enabling account of the key understanding or insight behind a given contribution, and (iii) experimental evidence that is not only contrasted with the state-of-the-art, but also meaningful in light of the driving application. Such failings can lead to reporting of spurious and misguided conclusions. For example, new ideas may appear promising in the context of a weak experimental testbed, but in reality do not advance the state of the art. The resulting inefficiencies can be detrimental to the entire research community. We draw on several models (chiefly from the metaheuristics community) [5] for experimental research and reporting in the area of heuristics for hard problems, and suggest that such practices can be adopted within the VLSI CAD community. Our focus is on hypergraph partitioning. 1 Introduction It is well-...

Netlist partitioning is an important and well studied problem. In this paper, a linear time partitioning approach based on iterative deletion is presented. We use the partitioning problem to allow a fair comparison of the iterative deletion approach with well known iterative improvement methods. For partitioning problems with a range of edge weights, and for multi-way partitioning, the iterative deletion approach can outperform the iterative improvement method. The algorithmic approach is flexible and can support complex cost functions directly. 1.

. We discuss the implementation and evaluation of move-based hypergraph partitioning heuristics in the context of VLSI design applications. Our first contribution is a detailed software architecture, consisting of seven reusable components, that allows flexible, efficient and accurate assessment of the practical implications of new move-based algorithms and partitioning formulations. Our second contribution is an assessment of the modern context for hypergraph partitioning research for VLSI design applications. In particular, we discuss the current level of sophistication in implementation know-how and experimental evaluation, and we note how requirements for real-world partitioners -- if used as motivation for research -- should affect the evaluation of prospective contributions. We then use two "implicit decisions" in the implementation of the Fiduccia-Mattheyses [20] heuristic to illustrate the difficulty of achieving meaningful experimental evaluation of new algorithmic ideas. Fina...

The balanced partitioning problem divides the nodes of a [hyper]graph into groups of approximately equal weight (i.e., satisfying balance constraints) while minimizing the number of [hyper]edges that are cut (i.e., adjacent to nodes in different groups). Classic iterative algorithms use the pass paradigm [24] in performing single-node moves [16, 13] to improve the initial solution. To satisfy particular balance constraints, it is usual to require that intermediate solutions satisfy the constraints. Hence, many possible moves are rejected. Hypergraph partitioning heuristics have been traditionally proposed for and evaluated on hypergraphs with unit node weights only. Nevertheless, many real-world applications entail varying node weights, e.g., VLSI circuit partitioning where node weight typically represents cell area. Even when multilevel partitioning [3] is performed on unit-node-weight hypergraphs, intermediate clustered hypergraphs have varying node weights. Nothing prevents the use...