Interprocessor communication (PC) overheads have emerged as the major performance limitation in parallel processing systems, due to the transmission delays, synchronization overheads, and conflicts for shared communication resources created by data exchange. Accounting for these overheads is essential for attaining efficient hardware utilization. This thesis introduces two new compile-time heuristics for scheduling precedence graphs onto multiprocessor architectures, which account for interprocessor communication overheads and interconnection constraints in the architecture. These algorithms perform scheduling and routing simultaneously to account for irregular interprocessor interconnections, and schedule all communications as well as all computations to eliminate shared resource contention. The first technique, called dynamic-level scheduling, modifies the classical HLFET list scheduling strategy to account for IPC and synchronization overheads. By using dynamically changing priorities to match nodes and processors at each step, this technique attains an equitable tradeoff between load balancing and interprocessor communication cost. This method is fast, flexible, widely targetable, and displays promising perforrnance. The second technique, called declustering, establishes a parallelism hierarchy upon the precedence graph using graph-analysis techniques which explicitly address the tradeoff between exploiting parallelism and incurring communication cost. By systematically decomposing this hierarchy, the declustering process exposes parallelism instances in order of importance, assuring efficient use of the available processing resources. In contrast with traditional clustering schemes, this technique can adjust the level of cluster granularity to suit the characteristics of the specified architecture, leading to a more effective solution.

Ptolemy is an environment for simulation, prototyping, and software synthesis for heterogeneous systems. It uses modern object-oriented software technology (in C++) to model each subsystem in a natural and efficient manner, and to integrate these subsystems into a whole. The objectives of Ptolemy encompass practically all aspects of designing signal processing and communications systems, ranging from algorithms and communication strategies, through simulation, hardware and software design, parallel computing, and generation of real-time prototypes. In this paper we will introduce the software synthesis aspects of the Ptolemy system. The environment presented here is both modular and extensible. Ptolemy allows the user to choose among various single- or multiple-processor schedulers. 1.0 Introduction Practical signal processing systems today are rarely implemented without software or firmware, even at the ASIC level. Programmable DSPs, in particular, form the heart of many implementati...

GLOBECOM, Dallas, Texas, November I989 completely addressed, either in the deterministic scheduling literature or in the multiprocessor systems literature. This paper will attempt to define these. Real-time digital signal processing often requires multiple processors. We assume the description of the program to be scheduled is a Unfortunately, in most practical situations, partitioning of DSP applica- dataflow graph, signal flow graph, or block diagram. Language classes tions for execution on multiple programmable Processors is ad-hoc. that are efficiently translated into dataflow graphs include functional, Automatic schedulers either (1) add unacceptable Cost to the implementation Or (2) address only a subset of applications. This Paper applicative, and single-assignment. In a dataflow graph the nodes, or actors, are functions that operate on data passed through the arcs. The explores the possibilities for automatic schedulers that result in IOW model is data-driven, in that actors fire (or perform their computation), imP1emenQfion Cost and Can target a broad class of DSP applications. when sufficient data is available on their input arcs. The role of the We Can define four classes of scheduling strategies, (1) fully dynamic, scheduler is simply to determine when to fire actors and on which pro-(2) static assiPment, (3) self-timed, and (4) fully static. Moving from cessor. The actors may have arbitrary granularity, meaning that they (1) to (4). more scheduling activity is Performed at compile time and less at run time. This Paper argues that for most DSP applications, self-timed scheduling is the most attractive. may represent atomic operations, such as addition and multiplication, or much more elaborate operations, such as transforms or digital filters. We assume that no attempt will be made to exploit concurrency within an actor, so that the scheduler only needs to operate on the dataflow 1.

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This paper reviews and extends an analytical model for the behavior of dataflow graphs with data-dependent control flow. The number of tokens produced or consumed by each actor is given as a symbolic function of the Booleans in the system. Long-term averages can be analyzed to determine consistency of token flow rates. Short-term behavior can be analyzed to construct an annotated schedule, or a static schedule that annotates each firing of an actor with the Boolean conditions under which that firing occurs. Necessary and sufficient conditions for bounded-length schedules, as well as sufficient conditions for determining that a dataflow graph can be scheduled in bounded memory are given. Annotated schedules can be used to generate efficient implementations of the algorithms described by the dataflow graphs. 1. Introduction The principal strength of dataflow graphs is that they do not over-specify an algorithm by imposing unnecessary sequencing constraints between operators. Instead, th...

Memorandum UCB/ERL M05/22 Earlier versions: • UCB/ERL M04/16 UCB/ERL M03/28 UCB/ERL M02/23 UCB/ERL M99/40 UCB/ERL M01/12

ations for the Motorola DSP96000 Family", M.S. Report, Plan II, EECS Dept., UC Berkeley, CA 94720, May, 1992. R-4 U. C. Berkeley Department of EECS plinary Course", Proc. of IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, vol. VI, pp. 45-48, Adelaide, Australia, April, 1994. [Lee94b] E. A. Lee, "Dataflow Process Networks," Electronics Research Laboratory Memorandum number UCB/ERL M94/53, University of California, Berkeley, CA 94720, July 1994. Also available at URL htttp://ptolemy.eecs.berkeley. edu. [Mes84a] D. G. Messerschmitt, "A Tool for Structured Functional Simulation", IEEE Journal on Selected Areas in Communications, vol. 2, no. 1, pp. 137-147, January, 1984. [Mes84b] D. G. Messerschmitt, "Structured Interconnection of Simulation Programs", Proc. of Globecom, Nov., 1984, vol. 2, pp. 808-811, Atlanta, Georgia. [Mur93] P. K. Murthy, "Multiprocessor DSP Code Synthesis in Ptolemy", Memorandum No. UCB/ERL M

This project explores design methodology for simulation and realtime parallel computation for applications using digital signal processing. The goal is to facilitate rapid prototyping of complex algorithms by developing tools that are both efficient in their use of hardware and easy for an algorithm designer to learn and use. In previous years, we have succeeded with a class of applications with deterministic control structure. This year, we have focussed on a broader class of applications involving run-time decisions and asynchronous real-time operations. The overall research problem divides into investigating human interfaces for specifying real-time systems (the language), developing algorithms for automated implementation (the compilation), and developing suitable target architectures (the architecture). The project has so far been extremely productive. Two versions of the Ptolemy software system have been widely distributed.

This paper builds upon research by Lee [1] concerning the token flow model, an analytical model for the behavior of dataflow graphs with data-dependent control flow, by analyzing the properties of cycles of the schedule: sequences of actor executions that return the graph to its initial state. Necessary and sufficient conditions are given for the existence of a bounded cyclic schedule, as well as sufficient conditions for execution of the graph in bounded memory. The techniques presented in this paper apply to a more general class of dataflow graphs than existing methods. MOTIVATION Dataflow graphs have proven to be an effective representation for problems in digital signal processing, both because the representation is natural for DSP researchers and because the representation exposes the parallelism of the algorithm and imposes minimal constraints on the order of its evaluation. Since the representation does not over-constrain the order of operations, a scheduler has the freedom it ...

This paper describes a multiprocessor machine for realtime Digital Signal Processing that uses commercial programmable DSP chips. The architecture is a shared memory, single shared bus parallel processor designed to run signal processing tasks that can be statically scheduled. The design is based on the architecture proposed in [1]. A prototype has since been built. The implementation details and performance results are discussed here.