ii An important trend in the design of digital cameras is the integration of capture and processing onto a single CMOS chip. Although integrating the components of a digital camera system onto a single chip significantly reduces system size and power, it does not fully exploit the potential advantages of integration. We argue that a key advantage of integration is the ability to exploit the high speed imaging capability of CMOS image sensors to enable new applications and to improve the performance of existing still and video processing applications. The idea is to capture frames at much higher frame rates than the standard frame rate, process the high frame rate data on chip, and output the video sequence and the application specific data at standard frame rate. In the first part of the dissertation we discuss two applications of this idea. The first is optical flow estimation, which is the basis for many video applications. We present a method for obtaining high accuracy optical flow estimates at a standard

Two techniques for performing pixel level analog to digital conversion (ADC) are reviewed. The first is an oversampling technique which uses a one bit first order Ez modulator for each 2 x 2 block of pixels to directly convert photocharge to bits. Each modulator is implemented using 17 transistors. The second technique is a Nyquist rate multi—channel--bit—serial (MCBS) ADC. The technique uses successive comparisons to convert the pixel voltage to bits. Results obtained from implementations of these ADC techniques are presented. The techniques are compared based on size, charge handling capacity, FPN, noise sensitivity, data throughput, quantization, memory/processing, and power dissipation requirements for both visible and JR imagers. From the comparison it appears that the L\ ADC is better suited to JR imagers, while the MCBS ADC is better suited to imagers in the visible range.

Techniques for characterizing CCD imagers have been developed over many years. These techniques have been recently modified and extended to CMOS PPS and APS imagers. With the scaling of CMOS technology, an increasing number of transistors can be added to each pixel. A promising direction to utilize these transistors is to perform pixel level ADC. The authors have designed and protoyped two imagers with pixel level Nyquist rate ADC. The ADCs operate in parallel and output data one bit at a time. The data is read out of the imager array one bit plane at a time in a manner similar to a digital memory. Existing characterization techniques could not be directly used for these imagers, however, since there is no facility to read out the analog pixel values before ADC, and the ADC resolution is limited to only 8 bits. Fortunately. the ADCs are fully testable electrically without the need for any light or optics. This makes it possible to obtain the ADC transfer curve, which greatly simplifies characterization. In this paper we describe how we characterize our pixel level ADC imagers. To estimate QE, we measure the imager photon to DN transfer curve and the the ADC transfer curve. We find that both curves are quite linear. Using an estimate of the sense node capacitance we then estimate sensitivity, and QE. To estimate FPN we model it as an outcome of the sum of two uncorrelated random processes, one representing the ADC FPN, and the other representing the photodetector FPN, and develop estimators for the model parameters form imager data under uniform illumination. We report characterization results for a 640×512 imager, which was fabricated in a 0.35µm standard digital CMOS process.

Most of today's video and digital cameras use CCD image sensors, where the electric charge collected by the photodetector array during exposure time is serially shifted out of the sensor chip resulting in slow readout speed and high power consumption. Recently developed CMOS image sensors, by comparison, are read out non-destructively and in a manner similar to a digital memory and can thus be operated at very high frame rates. A CMOS image sensor can also be integrated with other camera functions on the same chip ultimately leading to a single-chip digital camera with very compact size, low power consumption and additional functionality. CMOS image sensors, however, generally su#er from lower dynamic range than CCDs due to their high read noise and non-uniformity. Moreover, as sensor design follows CMOS technology scaling, well capacity will continue to decrease, eventually resulting in unacceptably low SNR.

Analysis results demonstrate that multiple sampling can achieve consistently higher signal-to-noise ratio at equal or higher dynamic range than using other image sensor dynamic range enhancement schemes such as well capacity adjusting. Implementing multiple sampling, however, requires much higher readout speeds than can be achieved using typical CMOS active pixel sensor (APS). This paper demonstrates, using a 640 222 512 CMOS image sensor with 8-b bit-serial Nyquist rate analog-todigital converter (ADC) per 4 pixels, that pixel-level ADC enables a highly flexible and efficient implementation of multiple sampling to enhance dynamic range. Since pixel values are available to the ADC's at all times, the number and timing of the samples as well as the number of bits obtained from each sample can be freely selected and read out at fast SRAM speeds. By sampling at exponentially increasing exposure times, pixel values with binary floating-point resolution can be obtained. The 640 222 512 ...

We developed a simulation model of an integrated CMOS-based imaging platform for use with bioluminescent DNA microarrays. We formulate the complete kinetic model of ATP based assays and luciferase label-based assays. The model first calculates the number of photons generated per unit time, i.e., photon flux, based upon the kinetics of the light generation process of luminescence probes. The photon flux coupled with the system geometry is then used to calculate the number of photons incident on the photodetector plane. Subsequently the characteristics of the imaging array including the photodetector spectral response, its dark current density, and the sensor conversion gain are incorporated. The model also takes into account different noise sources including shot noise, reset noise, readout noise and fixed pattern noise. Finally, signal processing algorithms are applied to the image to enhance detection reliability and hence increase the overall system throughput. We will present simulations and preliminary experimental results.

enhancement circuit using non-linear processing curve