ion and Specification Using FSMs Although there is a variety of ways to specify a protocol model, we are interested in methodologies that employ finite state machines (FSMs) to form protocol models. Because cache protocols are essentially composed of component processes such as memory and cache controllers that exchange messages and respond to "events" generated by processors, a finite state machine model with such "events" as its inputs is a natural model. Specifically, we focus on verifying cache protocols where the behavior of an individual protocol component C is modeled as a finite state machine [FSM.sub.c] and the protocol machine is composed of all [FSM.sub.c]s. Inputs to these machines are processor-generated events and messages for maintaining data consistency. In general, the protocol models are abstracted representations. They are often kept simple to make the complexity of verification manageable, while preserving properties of interest. It is clear that the quality of a ve...

Directory-based coherence protocols are so complex that verification techniques based on automated procedures are required to establish their correctness. State enumeration approaches are well-suited to the verification of cache protocols but they face the problem of state space explosion, leading to unacceptable verification time and memory consumption even for very small system configurations. In our previous work, we have introduced a verification methodology based on a symbolic state model of the system to verify. In this study, we apply this methodology to a write-invalidate, full-map directorybased coherence protocol for non-FIFO interconnection networks --i.e. networks in which the order of messages between two nodes is not preserved from source to destination. We develop the concepts and notations to verify some properties of the protocol with a symbolic state model (SSM). We compare the verification with SSM to the verification with the Stanford Murj system and show that SSM i...

In a cache-coherent, shared-memory multiprocessor system, data consistency among cached copies can be delayed until synchronization points under relaxed memory consistency models. Some protocols called delayed consistency protocols take advantage of this flexibility to reduce cache miss rates and memory traffic. However, they are very complex and validating their correctness, even at the behavior level, is a challenge. We have successfully applied a new verification tool to verify the delayed consistency protocol at the behavior level. The method is called SSM [22] for Symbolic State Model. The contribution of this paper, besides verifying the protocol, is to demonstrate how to deal with relaxed memory models and latency tolerance hardware in the context of SSM. 1

Field-Programmable Gate Arrays is an emerging technology which promises easy hardware reconfigurability by software at low cost. Entire systems can be built in which some parts are programmable. Such systems implement various architectures. Each architecture prototype is a detailed hardware implementation of the architecture -- including I/O-- on which complex software systems can be ported. We have built a multiprocessor emulator called RPM --Rapid Prototyping engine for Multiprocessor systems. The second version of the hardware called RPM-2 is up and running. In this paper, we present the design and the performance of our first emulator, a cache-coherent non uniform memory access multiprocessor (CC-NUMA). 1. Introduction There are currently many competing ideas to implement multiprocessor systems and some of them have been prototyped in hardware. However, hardware prototypes take too long to build and are very expensive. By the time a hardware prototype really works it is often obs...

Field-Programmable Gate Arrays is an emerging technology which promises easy hardware reconfigurability by software at low cost. Entire systems can be built in which some parts are easily programmable. Such systems are flexible hardware platforms or emulators, which are then tailored to implement various architectures. The performance of these architectures can be compared on the same hardware substrate. Besides having a large speedup advantage over software simulation, the emulator is a detailed hardware implementation of the architecture --including I/O-- on which complex software systems can be run without code instrumentation and it is a more convincing proof of concept. On the other hand it is much more cost-effective than a full-fledged prototype. We have built a multiprocessor emulator called RPM --Rapid Prototyping engine for Multiprocessor systems. RPM can emulate various configurations of shared-memory and message-passing systems. The bandwidth and latency of various componen...

In this paper, we present a comprehensive survey of various approaches for the verification of cache coherence protocols based on state enumeration, (symbolic) model checking and symbolic state models. Since these techniques search the state space of the protocol exhaustively, the amount of memory required to manipulate the state information and the verification time grow very fast with the number of processors and the complexity of the protocol mechanisms. To be successful for systems of arbitrary complexity, a verification technique must solve this so-called state space explosion problem. The emphasis of our discussion is on the underlying theory in each method to handle the state space explosion problem, and to formulate and check the safety properties (e.g., data consistency) and the liveness properties (absence of deadlock and livelock). We compare the efficiency and discuss the limitations of each technique in terms of memory and computation time. Also, we discuss issu...