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102
Efficient construction of pipelined multibittrie RouterTables
 IEEE Trans. Comput
, 2003
"... Efficient algorithms to construct multibit tries suitable for pipelined routertable applications are developed. We first enhance the 1phase algorithm of Basu and Narlikar [1] obtaining a 1phase algorithm that is 2.5 to 3 times as fast. Next we develop 2phase algorithms that not only guarantee to ..."
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Efficient algorithms to construct multibit tries suitable for pipelined routertable applications are developed. We first enhance the 1phase algorithm of Basu and Narlikar [1] obtaining a 1phase algorithm that is 2.5 to 3 times as fast. Next we develop 2phase algorithms that not only guarantee to minimize the maximum perstage memory but also guarantee to use the least total memory subject to the former constraint. Our 2phase algorithms not only generate better pipelined trees than generated by the 1phase algorithm but they also take much less time. A node pullup scheme that guarantees no increase in maximum perstage memory as well as a partitioning heuristic that generates pipelined multibit tries requiring less maximum perstage memory than required by the tries obtained using the 1phase and 2phase algorithms also are proposed.
Using a Large Linguistic Ontology for Internetbased Retrieval of ObjectOriented Components
 In Proceedings of 1997 Conference on Software Engineering and Knowledge Engineering. Madrid, Knowledge Systems Institute
, 1997
"... this paper adopts a language of limited expressiveness, privileging the simplicity of use as the most important requirement. We adopt a very simple graph structure for representing both queries and component data, but  differently from most of current systems  we do not assume the user to have f ..."
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this paper adopts a language of limited expressiveness, privileging the simplicity of use as the most important requirement. We adopt a very simple graph structure for representing both queries and component data, but  differently from most of current systems  we do not assume the user to have familiarity with the vocabulary used for component encoding, relying on a large linguistic ontology like Sensus [Swartout et al. 1996] to perform the match between queries and data. In the encoding phase (which we assume to be a manual process supported by an interactive environment), a software analyst describes a component by a simple graph where nodes and arcs are labelled with English words. Since binary relations are not usually denoted by nouns, a special semantics is adopted for this graph, which is called Lexical Semantic Graph. English nouns appearing in the graph are recognized by a lexical interface based on Wordnet [Miller 1995], which asks the analyst to choose among possibly different senses associated to each word. The graph of words is therefore translated into a graph of senses, each one corresponding to a node in the Sensus ontology. The query graph is built by the user in a similar way, but the words chosen and the corresponding senses can be of course different, as well as the structure of the graph. Conceptually, the search process implements a graph matching algorithm, returning the identifiers of all components whose description is subsumed by the query. In the following section, we describe the main design choices of a project on software retrieval currently going on at Corinto 1 , a research consortium established to study and promote objectoriented technology. In section 3 we present the encoding and retrieval process in some detail, with the help of...
Compact DAG Representation and its Dynamic Scheduling
 JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
, 1999
"... Scheduling large task graphs is an important issue in parallel computing. In this paper we tackle the two following problems : (1) how to schedule a task graph, when it is too large to t into memory? (2) How to build a generic program such that parameter values of a task graph can be given at runti ..."
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Scheduling large task graphs is an important issue in parallel computing. In this paper we tackle the two following problems : (1) how to schedule a task graph, when it is too large to t into memory? (2) How to build a generic program such that parameter values of a task graph can be given at runtime? Our answers feature the parameterized task graph (PTG), which is a symbolic representation of the task graph. We propose a dynamic scheduling algorithm which takes a PTG as an entry and allows to generate a generic program. We present a theoritical study which shows that our algorithm nds good schedules for coarse grain task graphs, has a very low memory cost and a low computational complexity. When the average number of operations of each task is large enough, we prove that the scheduling overhead is negligible with respect to the makespan. We also provide experimental results that demonstrate the feasibility of our approach using several computeintensive kernels found in numerical s...
An ObjectOriented Framework For File Systems
 PH.D. THESIS IN PREPARATION, UNIVERSITY OF ILLINOIS AT URBANACHAMPAIGN
, 1992
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Nearcritical path analysis of program activity graphs
 Proceedings of the 2nd International Workshop on Modeling, Analysis, and Simulation on Computer and Telecommunications Systems
, 1994
"... ..."
Succinct representation of static packet classifiers
, 2006
"... We develop algorithms for the compact representation of the 2dimensional tries that are used for Internet packet classification. Our compact representations are experimentally compared with competing compact representations for multidimensional packet classifiers and found to simultaneously reduce ..."
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Cited by 6 (5 self)
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We develop algorithms for the compact representation of the 2dimensional tries that are used for Internet packet classification. Our compact representations are experimentally compared with competing compact representations for multidimensional packet classifiers and found to simultaneously reduce the number of memory accesses required for a lookup as well as the memory required to store the classifier. 1
Engineering 'Unbounded' Reusable Ada Generics
 Proceedings of the Tenth National Conference on Ada Technology, ANCOST, Inc
, 1992
"... Most current programming languages (including Ada) provide some means of allowing the programmer to dynamically allocate and deallocate heap storage. This permits construction of “unbounded ” abstract data types, e.g., stacks, queues, oneway lists, etc. Unfortunately, the addition of dynamically al ..."
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Cited by 4 (1 self)
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Most current programming languages (including Ada) provide some means of allowing the programmer to dynamically allocate and deallocate heap storage. This permits construction of “unbounded ” abstract data types, e.g., stacks, queues, oneway lists, etc. Unfortunately, the addition of dynamically allocated storage to the implementation of abstract data types is a complicated business. Unless special care is taken, it can lead to problems of storage leaks, dangling references, unwanted aliasing, and unexpected lengthy execution times (due to storage allocation and reclamation), among others. We propose a specific discipline for avoiding these problems. 1.
Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits
, 1990
"... Directed acyclic graphs (dags) are often used to model circuits. Path lengths in such dags represent circuit delays. In the vertex splitting problem, the objective is to determine a minimum number of vertices to split so that the resulting dag has no path of length d. This problem has application to ..."
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Cited by 4 (0 self)
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Directed acyclic graphs (dags) are often used to model circuits. Path lengths in such dags represent circuit delays. In the vertex splitting problem, the objective is to determine a minimum number of vertices to split so that the resulting dag has no path of length d. This problem has application to the placement of flipflops in partial scan designs, placement of latches in pipelined circuits, placement of signal boosters in lossy circuits and networks, etc. Several simplified versions of this problem are shown to be NPhard. A linear time algorithm is obtained for the case when the dag is a tree. A backtracking algorithm and heuristics are developed for general dags and experimental results using dags obtained from ISCAS benchmark circuits are obtained.
Multicast ATM Switches Based on Input Cells Scheduling
, 1999
"... this paper, we propose a prescheduling mechanism to precede the multicast switch. This mechanism will completely eliminate the problems mentioned above. Two architectures are designed to implement this mechanism. Analysis and simulations show that our design performs quite well. ..."
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Cited by 4 (1 self)
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this paper, we propose a prescheduling mechanism to precede the multicast switch. This mechanism will completely eliminate the problems mentioned above. Two architectures are designed to implement this mechanism. Analysis and simulations show that our design performs quite well.
Design of Hyper States for ReducedState Sequence Estimation
 In Proceedings of the International Conference on Communications (ICC'95
"... A new method for the design of hyper states for reducedstate sequence estimation of trellis coded signals is proposed. Examples are given for trellis coded modulation (TCM) over channels with intersymbol interference (ISI). The complexity of the super trellis resulting from the combination of the ..."
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A new method for the design of hyper states for reducedstate sequence estimation of trellis coded signals is proposed. Examples are given for trellis coded modulation (TCM) over channels with intersymbol interference (ISI). The complexity of the super trellis resulting from the combination of the TCM and ISI trellises is reduced by an algorithm that applies set partitioning principles to the set of super states. The method often allows to achieve asymptotic optimality at a low level of complexity. Simulations and comparisons with other methods show the superior performance of the proposed class of reducedstate sequence estimators (RSSE).