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Threshold Network Synthesis and Optimization and Its Application to Nanotechnologies
 IEEE Transaction On ComputerAided Design Of Integrated Circuits And Systems
, 2005
"... Abstract — We propose an algorithm for efficient threshold network synthesis of arbitrary multioutput Boolean functions. Many nanotechnologies, such as resonant tunneling diodes (RTDs), quantum cellular automata (QCA), and single electron tunneling (SET), are capable of implementing threshold logic ..."
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Abstract — We propose an algorithm for efficient threshold network synthesis of arbitrary multioutput Boolean functions. Many nanotechnologies, such as resonant tunneling diodes (RTDs), quantum cellular automata (QCA), and single electron tunneling (SET), are capable of implementing threshold logic efficiently. The main purpose of this work is to bridge the current wide gap between research on nanoscale devices and research on synthesis methodologies for generating optimized networks utilizing these devices. While functionallycorrect threshold gates and circuits based on nanotechnologies have been successfully demonstrated, there exists no methodology or design automation tool for general multilevel threshold network synthesis. We have built the first such tool, ThrEshold Logic Synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with 56 multioutput benchmarks indicate that, compared to traditional logic synthesis, upto 80.0 % and 70.6 % reduction in gate count and interconnect count, respectively, is possible with the average being 22.7 % and 12.6%, respectively. Furthermore, the synthesized networks are wellbalanced structurally. The novelty of this work lies in the introduction of the first comprehensive synthesis methodology and tool for general multilevel threshold logic design. Index Terms — Design automation, logic synthesis, QCA, RTD, threshold networks.
Yakovlev: Towards Power Elastic Systems through Concurrency Management Towards Power Elastic Systems through Concurrency Management
"... Power constrained systems, di erent from traditional low power systems, are becoming more recognized. The operation of these systems is not constrained only by the availability of traditional resources such as software or hardware, but is limited by applicable power. Designing such systems poses new ..."
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Power constrained systems, di erent from traditional low power systems, are becoming more recognized. The operation of these systems is not constrained only by the availability of traditional resources such as software or hardware, but is limited by applicable power. Designing such systems poses new challenges. We meet these challenges by departing from the classical low power design approach and taking a power elastic system view. In this paper we present an architectural level solution based on realtime feedback control to t system operation into power constraint pro les. Investigations into concurrency management as the main method for such realtime control are carried out. As part of this methodology we present a new approach, called `soft arbitration', which can be applied to solving the problem of energy resource allocation and power capping. This work provides a concrete foundation for the power elastic methodology through developing a set of modelling, analysis, design and implementation techniques covering both theoretical and practical issues. 1
Synthesis and optimization of threshold logic networks with application to nanotechnologies
 in Design, Automation and Test in Europe Conference and Exhibition
, 2004
"... Abstract — We propose an algorithm for efficient threshold network synthesis of arbitrary multioutput Boolean functions. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and research on the development of synthesi ..."
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Abstract — We propose an algorithm for efficient threshold network synthesis of arbitrary multioutput Boolean functions. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and research on the development of synthesis methodologies to generate optimized networks utilizing these devices. Many nanotechnologies, such as resonant tunneling diodes (RTD) and quantum cellular automata (QCA), are capable of implementing threshold logic. While functionally correct threshold gates have been successfully demonstrated, there exists no methodology or design automation tool for general multilevel threshold network synthesis. We have built the first such tool, ThrEshold Logic Synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with about 60 multioutput benchmarks were performed, though the results of only 10 of them are reported in this paper because of space restrictions. They indicate that up to 77 % reduction in gate count is possible when utilizing threshold logic, with an average reduction being 52%, compared to traditional logic synthesis. Furthermore, the synthesized networks are wellbalanced, and hence delayoptimized. I.
A new decomposition algorithm for threshold synthesis and generalization of boolean functions. Circuits and Systems I: Regular Papers
 IEEE Transactions on
, 2008
"... Abstract—A new algorithm for obtaining efficient architectures composed of threshold gates that implement arbitrary Boolean functions is introduced. The method reduces the complexity of a given target function by splitting the function according to the variable with the highest influence. The proced ..."
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Abstract—A new algorithm for obtaining efficient architectures composed of threshold gates that implement arbitrary Boolean functions is introduced. The method reduces the complexity of a given target function by splitting the function according to the variable with the highest influence. The procedure is iteratively applied until a set of threshold functions is obtained, leading to reduced depth architectures, in which the obtained threshold functions form the nodes and a AND or OR function is the output of the architecture. The algorithm is tested on a large set of benchmark functions and the results compared to previous existing solutions, showing a considerable reduction on the number of gates and levels of the obtained architectures. An extension of the method for partially defined functions is also introduced and the generalization ability of the method is analyzed. Index Terms—Circuit complexity, generalization, linear separability, logic synthesis, threshold networks. I.
An automatic test pattern generation framework for combinational threshold logic networks
 in Proc. Int. Conf. Computer Design
, 2004
"... Abstract — We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs) and quantum cellular automata (QCA), implement threshold ..."
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Abstract — We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs) and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this type of logic. We have built the first automatic test pattern generator and fault simulator for threshold logic which has been integrated on top of an existing computeraided design (CAD) tool. These exploit new fault collapsing techniques we have developed for threshold networks. We perform fault modeling to show that many cuts and shorts in RTDbased threshold gates are equivalent to stuckat faults at the inputs and output of the gate. Experimental results with the MCNC benchmarks indicate that test vectors were found for all testable stuckat faults in their threshold network implementations. I.
On Kolmogorov’s Superpositions: Novel Gates and Circuits for Nanoelectronics?
"... Based on explicit numerical constructions for Kolmogorov’s superpositions (KS) linear size circuits implementing arbitrary Boolean functions (BFs) are possible. Because classical Boolean as well as threshold logic (TL) implementations, require exponential size in the worst case, it follows that, si ..."
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Based on explicit numerical constructions for Kolmogorov’s superpositions (KS) linear size circuits implementing arbitrary Boolean functions (BFs) are possible. Because classical Boolean as well as threshold logic (TL) implementations, require exponential size in the worst case, it follows that, sizeoptimal solutions for implementing arbitrary BFs should rely (at least partly) on KSinspired gates (KGs). In this paper, we examine BFs of three inputs in detail and show that even the size given by KS can be reduced when Boolean gates (BGs) could be optimally combined with KGs (low precision analog gates). This shows that there is room for improving on the synthesis of BFs. Finally, we will show that the size obtained when optimally combining BGs and KGs can be reduced even further if we are allowed to also use TL gates. Such systematic size reductions could help alleviate the challenging power consumption problem. They advocate for the design of KGs, as well as for the development of the theory, the algorithms, and the CAD tools that could take advantage of optimal combinations of different logic gates and design styles.
Threshold logic implementations: The early days
 PROC. MWSCAS’03
, 2003
"... This paper gives a brief account of the results on hardware implementations of threshold logic obtained starting from the forties. The solutions are sorted chronologically, by order of their publication date, although the order would be somehow different by submission date. Reviewing the many differ ..."
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This paper gives a brief account of the results on hardware implementations of threshold logic obtained starting from the forties. The solutions are sorted chronologically, by order of their publication date, although the order would be somehow different by submission date. Reviewing the many different solutions, we will identify those that have been enduring, and mention a few that have been long forgotten, but rediscovered a few decades later.
Serial Addition: Locally Connected Architectures
"... Abstract—This paper will briefly review nanoelectronic challenges while focusing on reliability. We shall present and analyze a series of CMOSbased examples for addition starting from the device level and moving up to the gate, the circuit, and the block level. Our analysis, backed by simulation re ..."
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Abstract—This paper will briefly review nanoelectronic challenges while focusing on reliability. We shall present and analyze a series of CMOSbased examples for addition starting from the device level and moving up to the gate, the circuit, and the block level. Our analysis, backed by simulation results, on comparing parallel and serial addition shows that serial adders are more reliable while also dissipating less. Their reliability can be improved by using reliabilityenhanced gates and/or other redundancy techniques (like e.g., multiplexing). Additionally, the architectural technique of shortcircuiting the outputs (of several redundant devices/gates/blocks) exhibits “vanishing ” voting and an inherent fault detection mechanism, as both transient and permanent faults could be detected based on current changes. The choice of CMOS is due to the broad design base available (but the ideas can be applied to other technologies), while addition was chosen due to its
Mapping a faulttolerant distributed algorithm to systems on chip
 In Digital System Design Architectures, Methods and Tools
, 2008
"... Systems on chip (SoC) have much in common with traditional (networked) distributed systems in that they consist of largely independent components with dedicated communication interfaces. Therefore the adoption of classic distributed algorithms for SoCs suggests itself. The implementation complex ..."
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Systems on chip (SoC) have much in common with traditional (networked) distributed systems in that they consist of largely independent components with dedicated communication interfaces. Therefore the adoption of classic distributed algorithms for SoCs suggests itself. The implementation complexity of these algorithms, however, significantly depends on the underlying failure models. In traditional softwarebased solutions this is normally not an issue, such that the most unconstrained, namely the Byzantine, failure model is often applied here. Our case study of a hardwareimplemented tick synchronization algorithm shows, however, that in an SoCimplementation substantial hardware savings can result from restricting the failure model to benign failures (omissions, crashes). On the downside, it turns out that such restricted failure models have a fairly poor coverage with respect to the hardware faults occurring in practice, and that additional measures to enforce these restrictions may entail an implementation overhead that outweighs the gain obtained in the implementation of a simpler algorithm. As a remedy we investigate the potential of failure transformation in this context and show that this technique may indeed yield an optimized overall solution. 1.
Optimal synthesis of Boolean functions by threshold functions
"... Abstract. We introduce a new method for obtaining optimal architectures that implement arbitrary Boolean functions using threshold functions. The standard threshold circuits using threshold gates and weights are replaced by nodes computing directly a threshold function of the inputs. The method deve ..."
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Abstract. We introduce a new method for obtaining optimal architectures that implement arbitrary Boolean functions using threshold functions. The standard threshold circuits using threshold gates and weights are replaced by nodes computing directly a threshold function of the inputs. The method developed can be considered exhaustive as if a solution exist the algorithm eventually will find it. At all stages different optimization strategies are introduced in order to make the algorithm as efficient as possible. The method is applied to the synthesis of circuits that implement a flipflop circuit and a multiconfigurable gate. The advantages and disadvantages of the method are analyzed. 1