Results 1  10
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12
N.Bhat, “Layout driven technology mapping
 Design Automation Conference
, 1991
"... Recent studies indicate that interconnections occupy more than hatf the total chip area and account for a significant part of the chip delay. In spite of this, most logic synthesis systems do not explicitly take the wiring into account during the optimization phase. Our work is a first step towards ..."
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Cited by 51 (17 self)
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Recent studies indicate that interconnections occupy more than hatf the total chip area and account for a significant part of the chip delay. In spite of this, most logic synthesis systems do not explicitly take the wiring into account during the optimization phase. Our work is a first step towards including wiring into the logic synthesis process. In this paper, we present Lily, a technology mapper integrated with MIS, which considers layout area and wire delay during the technology dependent phase of logic synthesis. Lily estimates the intercomection dependent contributions to circuit area and delay by referring to a dynamically updated global placement of the Boolean network. The update does not restrict the dynamic progr arnming approach adopted in technology mappers such as DAGON and MIS. Our algorithm has been implemented and preliminary results are encouraging. 1
On Wirelength Estimations for RowBased Placement
, 1998
"... Wirelength estimation in VLSI layout is fundamental to any predetailed routing estimate of timing or routability. In this paper, we develop efficient wirelength estimation techniques appropriate for wirelength estimation during topdown floorplanning and placement of cellbased designs. Our methods ..."
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Cited by 35 (10 self)
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Wirelength estimation in VLSI layout is fundamental to any predetailed routing estimate of timing or routability. In this paper, we develop efficient wirelength estimation techniques appropriate for wirelength estimation during topdown floorplanning and placement of cellbased designs. Our methods give accurate, lineartime approaches, typically with sublinear time complexity for dynamic updating of estimates (e.g., for annealing placement). Our techniques offer advantages not only for early online wirelength estimation during topdown placement, but also for a posteriori estimation of routed wirelength given a final placement. In developing these new estimators, we have made several contributions, including (i) insight into the contrast between regionbased and bounding boxbased RStMT estimation techniques; (ii) empirical assessment of the correlations between pin placements of a multipin net that is contained in a block; and (iii) new wirelength estimates that are functions of a...
Concurrent Logic Restructuring and Placement for Timing Closure
 in Proc. IEEE International Conference on Computer Aided Design
, 1999
"... ABSTRACT: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of supercells along the critical paths and then generates the set of noninferior remapping solutions for each supercell. The best mapping and placement solu ..."
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Cited by 15 (0 self)
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ABSTRACT: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of supercells along the critical paths and then generates the set of noninferior remapping solutions for each supercell. The best mapping and placement solutions for all supercells are obtained by solving a generalized geometric programming (GGP) problem. The process of identifying and optimizing the critical paths is iterated until timing closure is achieved. Experimental results on a set of MCNC benchmarks demonstrate the effectiveness of our algorithm. I.
Simultaneous Gate Sizing and Placement
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2000
"... In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and op ..."
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Cited by 13 (3 self)
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In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. More precisely in each iteration, we perform three operations: a) reposition the immediate fanouts of the gates on the kmost critical paths; b) size down the immediate fanouts of the gates on the kmost critical paths; c) simultaneously reposition and resize the gates on the kmost critical paths. Each of these operations is formulated and solved as a mathematical program by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement. 1
BEARFP: A Robust Framework for Floorplanning
 INTERNATIONAL JOURNAL OF HIGH SPEED ELECTRONICS
, 1992
"... This paper presents a hierarchical floorplanning approach for macrocell layouts which is based on the bottomup clustering, shape function computation, and top down floorplan optimization with integrated global routing and pin assignment. This approach provides means for specifying and techniques fo ..."
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Cited by 7 (2 self)
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This paper presents a hierarchical floorplanning approach for macrocell layouts which is based on the bottomup clustering, shape function computation, and top down floorplan optimization with integrated global routing and pin assignment. This approach provides means for specifying and techniques for satisfying a wide range of constraints (physical, topological, timing) and is, therefore, able to generate floorplans for a number of different layout styles. A systematic and efficient optimization procedure during the selection of suitable floorplan patterns that integrates floorplanning, global routing and pin assignment, a new pin assignment technique based on linear assignment and driven by the global routing solution and floorplan topology, and an effective timingdriven floorplanning scheme are among the other novel features of the floorplanner. These techniques have been incorporated in BEARFP, a macrocell layout system developed at the University of California, Berkeley. Results on various placement and floorplanning benchmarks are quite good.
Worstcase ratios of networks in the rectilinear plane
 Networks
, 2000
"... For point sets in the rectilinear plane we consider the following five measures of the interconnect length and prove bounds on the worstcase ratio: minimum Steiner tree, minimum star, clique, minimum spanning tree, and bounding box. In particular, we prove that for any set of n points: (n − 1) time ..."
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Cited by 7 (3 self)
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For point sets in the rectilinear plane we consider the following five measures of the interconnect length and prove bounds on the worstcase ratio: minimum Steiner tree, minimum star, clique, minimum spanning tree, and bounding box. In particular, we prove that for any set of n points: (n − 1) times the shortest Steiner tree is less or equal to the clique unless n = 4; and the minimum spanning tree is less or equal to the shortest star unless n ∈ {3, 4, 5}. 1
Accuracy and Fidelity of Fast Net Length Estimates
 ACM VLSI Integration, the VLSI Journal
, 1997
"... Most popular tools for VLSI placementrelyonsometype of local search algorithm to iteratively refine a given placement solution. In such algorithms, it is necessary to evaluate the total amount of routing that a given placement will require. Typically, rectilinear Steiner tree heuristics are used ..."
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Cited by 5 (0 self)
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Most popular tools for VLSI placementrelyonsometype of local search algorithm to iteratively refine a given placement solution. In such algorithms, it is necessary to evaluate the total amount of routing that a given placement will require. Typically, rectilinear Steiner tree heuristics are used to estimate the routing length of a placement. When evaluating heuristics, researchers typically focus on their absolute accuracy,i.e., how nearly optimal are their solutions? However, here a more pertinent statistic is their relative accuracy,i.e. howlikely is it that a given heuristic will agree with the optimum on whichoftwo instances has the shorter routing? In this paper, we experimentally evaluate four popular net length estimation heuristics, with respect to both their absolute and relative accuracy as well as their speed. Keywords: rectilinear Steiner tree heuristics, accuracy, fidelity. 1 Introduction In electronic physical design automation, the placement problem is that o...
TimingDriven Placement for General Cell Layout
, 1990
"... In this paper we present a hierarchical technique for the timingdriven placement of the general cells. We assume that maximum interconnection delays for nets are given. We transform these timing constraints to net length constraints using technology and process dependent parameters, circuit specif ..."
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Cited by 4 (2 self)
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In this paper we present a hierarchical technique for the timingdriven placement of the general cells. We assume that maximum interconnection delays for nets are given. We transform these timing constraints to net length constraints using technology and process dependent parameters, circuit specific data such as input capacitance and output drivability, and the structural description of the circuit.. Next, we break the problem into a bottomup clustering phase and a topdown enumerative placement phase. We consider both the natural connectivities and the net length constraints during the bottomup phase in order to generate a hierarchical cluster tree. During the topdown placement phase, we place each node of the cluster tree so that the layout area and total interconnection length are minimized while satisfying the net length constraints.
The Steiner Tree Problem in Orientation Metrics
 J. Comp. Syst. Sci
, 1997
"... Given a set \Theta of ff i (i = 1; 2; : : : ; k) orientations (angles) in the plane, one can define a distance function which induces a metric in the plane, called the orientation metric [3]. In the special case where all the angles are equal, we call the metric a uniform orientation metric [2]. Spe ..."
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Cited by 3 (1 self)
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Given a set \Theta of ff i (i = 1; 2; : : : ; k) orientations (angles) in the plane, one can define a distance function which induces a metric in the plane, called the orientation metric [3]. In the special case where all the angles are equal, we call the metric a uniform orientation metric [2]. Specifically, if there are oe orientations, forming angles i oe ; 0 i oe \Gamma 1, with the xaxis, where oe 2 is an integer, we call the metric oe  metric. Note that the 2 metric is the wellknown rectilinear metric and the 1 corresponds to the Euclidean metric. In this paper, we will concentrate on the 3 metric. In the 2 metric, Hanan [1] shows that there exists a solution of the Steiner tree problem such that all Steiner points are on the intersections of grid lines formed by passing lines at directions i 2 ; i = 0; 1, through all demand points. But this is not true in the 3 metric. In this paper, we mainly prove the following theorem: Let P , Q and O i (i = 1; 2; : : : ; ...
M.Pedram “Gate sizing with controlled Displacement
 in Proceedings of international symposium on physical design
"... Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively ident ..."
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Cited by 2 (1 self)
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Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. All the operations are formulated and solved as mathematical programming problems by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches, which separate gate sizing from gate placement. 1