Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing or routability. In this paper, we develop efficient wirelength estimation techniques appropriate for wirelength estimation during topdown floorplanning and placement of cell-based designs. Our methods give accurate, linear-time approaches, typically with sublinear time complexity for dynamic updating of estimates (e.g., for annealing placement). Our techniques offer advantages not only for early on-line wirelength estimation during top-down placement, but also for a posteriori estimation of routed wirelength given a final placement. In developing these new estimators, we have made several contributions, including (i) insight into the contrast between region-based and bounding box-based RStMT estimation techniques; (ii) empirical assessment of the correlations between pin placements of a multi-pin net that is contained in a block; and (iii) new wirelength estimates that are functions of a...

In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. More precisely in each iteration, we perform three operations: a) reposition the immediate fan-outs of the gates on the k-most critical paths; b) size down the immediate fan-outs of the gates on the k-most critical paths; c) simultaneously reposition and resize the gates on the k-most critical paths. Each of these operations is formulated and solved as a mathematical program by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement. 1

For point sets in the rectilinear plane we consider the following five measures of the interconnect length and prove bounds on the worst-case ratio: minimum Steiner tree, minimum star, clique, minimum spanning tree, and bounding box. In particular, we prove that for any set of n points: (n − 1) times the shortest Steiner tree is less or equal to the clique unless n = 4; and the minimum spanning tree is less or equal to the shortest star unless n ∈ {3, 4, 5}. 1

Most popular tools for VLSI placementrelyonsometype of local search algorithm to iteratively refine a given placement solution. In such algorithms, it is necessary to evaluate the total amount of routing that a given placement will require. Typically, rectilinear Steiner tree heuristics are used to estimate the routing length of a placement. When evaluating heuristics, researchers typically focus on their absolute accuracy,i.e., how nearly optimal are their solutions? However, here a more pertinent statistic is their relative accuracy,i.e. howlikely is it that a given heuristic will agree with the optimum on whichoftwo instances has the shorter routing? In this paper, we experimentally evaluate four popular net length estimation heuristics, with respect to both their absolute and relative accuracy as well as their speed. Keywords: rectilinear Steiner tree heuristics, accuracy, fidelity. 1 Introduction In electronic physical design automation, the placement problem is that o...

Given a set \Theta of ff i (i = 1; 2; : : : ; k) orientations (angles) in the plane, one can define a distance function which induces a metric in the plane, called the orientation metric [3]. In the special case where all the angles are equal, we call the metric a uniform orientation metric [2]. Specifically, if there are oe orientations, forming angles i oe ; 0 i oe \Gamma 1, with the x-axis, where oe 2 is an integer, we call the metric oe - metric. Note that the 2 -metric is the well-known rectilinear metric and the 1 corresponds to the Euclidean metric. In this paper, we will concentrate on the 3 -metric. In the 2 -metric, Hanan [1] shows that there exists a solution of the Steiner tree problem such that all Steiner points are on the intersections of grid lines formed by passing lines at directions i 2 ; i = 0; 1, through all demand points. But this is not true in the 3 -metric. In this paper, we mainly prove the following theorem: Let P , Q and O i (i = 1; 2; : : : ; ...

This paper proposes new net criticality metrics and one pass design flow methodology for timing-driven physical design. The proposed net criticality metrics employ net parameters and bounds on net delays derived by the Minimax algorithm. The criticality metrics were mapped to weights in the Cadence Silicon Ensemble DSM Automatic Layout System and produced in one-pass layouts with the clock cycle approximately 27 % faster in average than without criticality evaluation. Criticality metrics are independent of layout tools producing actual placement and routing. Criticality calculation could be integrated with any layout system that allows weights for individual nets on the placement and routing steps. 1.

In this paper we present a hierarchical technique for the timing-driven placement of the general cells. We assume that maximum interconnection delays for nets are given. We transform these timing constraints to net length constraints using technology and process de-pendent parameters, circuit specific data such as input capacitance and output drivability, and the structural description of the circuit.. Next, we break the prob-lem into a bottom-up clustering phase and a topdown enumerative placement phase. We consider both the natural connectivities and the net length constraints during the bottom-up phase in order to generate a hi-erarchical cluster tree. During the top-down placement phase, we place each node of the cluster tree so that the layout area and total interconnection length are minimized while satisfying the net length constraints. 1