Results 11  20
of
70
Analysis of Thermal Noise and the Effect of Parasitics in the ChargePump Integrator
"... Abstract—The concept of using capacitive chargepumps to reduce the power consumption in switchedcapacitor (SC) integrators is further extended. It is shown that the chargepump (CP) integrator can be implemented using both opampbased and comparatorbased SC circuits and achieve significant power ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
Abstract—The concept of using capacitive chargepumps to reduce the power consumption in switchedcapacitor (SC) integrators is further extended. It is shown that the chargepump (CP) integrator can be implemented using both opampbased and comparatorbased SC circuits and achieve significant power savings. When the input sampling capacitor is split into two capacitors, the opampbased CP integrator ideally consumes 1/4 of the power of a conventional SC integrator, while maintaining almost the same thermal noise performance. An analytical expression for the inputreferred thermal noise of the CP integrator is derived and compared with the conventional integrator. The effect of parasitic capacitances on the CP integrator circuit is discussed. Inputreferred thermal noise simulation results are provided. I.
Deliverable D1.1.1 Analysis of major nonidealities of multibit oversampling converters
"... 2. Classification of the nonidealities 2 3. Integrator related nonidealities 3 3.1. Finite operational amplifier gain 5 ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
2. Classification of the nonidealities 2 3. Integrator related nonidealities 3 3.1. Finite operational amplifier gain 5
Analysis and Design of MultipleBit HighOrder \Sigma\Delta Modulator
 566 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 9, SEPTEMBER 2003 [13
, 1997
"... The highorder \Sigma\Delta modulator is an appropriate approach for highbandwidth, highresolution A/D conversion. However, nonideal effects such as the finite opamp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
The highorder \Sigma\Delta modulator is an appropriate approach for highbandwidth, highresolution A/D conversion. However, nonideal effects such as the finite opamp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable nonideal effects, we explore several multiplebit schemes, based on our CIQE highorder \Sigma\Delta architecture, to remove the nonideal deterioration. Design rules of these multiplebit schemes are developed and verified by extensive simulations. I. Introduction The A/D converter is an important element for digitalsignal processing systems. The cruxes of an A/D converter are high resolution for precise representation of the original signal and high bandwidth for fast processing. Conventional A/D architectures, e.g., flash, 2step flash, and successive approximation, are not suitable for highresolution applications because of the need of nearideal analog component...
A Low Oversampling Ratio 14b 500kHz ΔΣ ADC with a SelfCalibrated Multibit DAC
"... Deltasigma (\Delta\Sigma) analogtodigital converters rely on oversampling technique to achieve highresolution. By overcoming stability limitations and applying multibit quantization, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500 kHz deltasigma ADC ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
Deltasigma (\Delta\Sigma) analogtodigital converters rely on oversampling technique to achieve highresolution. By overcoming stability limitations and applying multibit quantization, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500 kHz deltasigma ADC is described that uses an oversampling ratio of only 16. A fourthorder embedded modulator, fourbit quantizer, and selfcalibrated DAC are used to achieve this performance. Although the highorder embedded architecture was previously thought to be unstable, it is shown that with proper design a robust system can be obtained. Circuit design and implementation in a 1.2¯m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date. 1 Introduction Deltasigma (\Delta\Sigma) analogtodigital converters are well suited for low f...
Scaling Input Signal Swings of Overloaded Integrators in Resonatorbased SigmaDelta Modulators
"... Abstract—Overloading of the integrators in loop filter of SigmaDelta modulators is a performance degrading factor in circuit implementations. In this paper, it is shown that in resonatorbased Â ∆ modulators scaling factors should be introduced in order to adjust the integrators ' input. A sys ..."
Abstract
 Add to MetaCart
Abstract—Overloading of the integrators in loop filter of SigmaDelta modulators is a performance degrading factor in circuit implementations. In this paper, it is shown that in resonatorbased Â ∆ modulators scaling factors should be introduced in order to adjust the integrators ' input. A systematic method is presented to calculate these scaling factors without modifying the noise and signal transfer functions. The effect of the scaling factors on circuit implementation is also discussed. Several examples are given to illustrate the influence of the scaling factors on the Â∆ performances depending on the order, architecture and number of bits of the quantizer. Figure 1. Feedforward architectures of SigmaDelta Modulators (CRFF) I.
MULTIBIT DELTASIGMA MODULATION TECHNIQUE FOR FRACTIONALN FREQUENCY SYNTHESIZERS
"... FractionalN frequency synthesis provides agile switching in narrow channel spacing systems and alleviates phaselocked loop (PLL) design constraints for phase noise and reference spur. The inherent problem of the fractionalN frequency synthesizer is that the periodic operation of the dualmodulus ..."
Abstract
 Add to MetaCart
FractionalN frequency synthesis provides agile switching in narrow channel spacing systems and alleviates phaselocked loop (PLL) design constraints for phase noise and reference spur. The inherent problem of the fractionalN frequency synthesizer is that the periodic operation of the dualmodulus divider produces spurious tones. Several techniques have been used to reduce spurious tones. Among those techniques, the deltasigma modulation method provides arbitrarily fine frequency resolution and makes the spurreduction scheme less sensitive to process and temperature variations since frequencies are synthesized by the digital modulation. This thesis proposes a multibit ∆−Σ modulation technique as a spur reduction method to enhance the overall synthesizer performance, and the oversampling modulator performance is analyzed with the consideration of practical design aspects for frequency synthesizers. A prototype fractionalN frequency synthesizer using a 3b thirdorder ∆−Σ modulator has been designed and implemented in 0.5µm CMOS. Synthesizing 900 MHz with 1Hz resolution, it exhibits an inband phase noise of92 dBc/Hz at 10kHz offset with a reference spur of less than95 dBc. Experimental results show that the proposed system
COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY
, 2004
"... Integration of analogtodigital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytic ..."
Abstract
 Add to MetaCart
Integration of analogtodigital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discretetime and continuoustime integration in voltagemode and in currentmode. For high resolution, superiority of switchedcapacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution. Keywords: Analog–digital conversion; sigma–delta modulation; signaltonoise analysis; low voltage CMOS; switched capacitors; switched current. 1.