and Computer Sciences

2. Classification of the nonidealities 2 3. Integrator related nonidealities 3 3.1. Finite operational amplifier gain 5

Behavioral-level performance modeling of analog and mixed-signal systems using support vector machines This paper presents a novel behavioral-level analog and mixedsignal (AMS) system performance modeling methodology using support vector machines (SVM). The method relies on linearly graded sub-spaces to model complex multi-dimensional performance spaces. A detailed evaluation of the method has been carried out for the purpose of potential use for AMS synthesis. The method has been applied to a complex nonideal 2 nd order Sigma-Delta modulator (SDM) and results show good accuracy of performance modeling and numerical efficiency. 1.

A major focus of recent RF transceiver IC designs has been to increase both the integration and adaptability to multiple RF communication standards. Performing channel selection on chip at baseband allows the use of high-integration receiver architectures, and enhances programmability to different channel bandwidths and dynamic range requirements of multiple RF standards. A wideband, high-dynamic range sigma-delta modulator can be used to digitize both the desired signal and potentially stronger adjacent-channel interferers. In the digital domain, the decimation filter following the ADC can be easily made programmable. A 4th-order sigma-delta ADC which is capable of adapting to GSM (cellular) and DECT (cordless) communication standards is described. The ADC achieves 14 bits of resolution at 128x oversampling ratio (200kS/s Nyquist rate) for GSM, and 12 bits of i resolution at 32x oversampling ratio (1.4MS/s Nyquist rate) for DECT. Power reduction strategies are developed at both the sigma-delta architecture and circuit design levels. The experimental prototype, fabricated in a 0.35μm CMOS process, dissipates 70mW from a 3.3V supply.

A single-chip implementation of a microinstrumentation system is presented. The chip incorporates voltage, current, and capacitive sensor interfaces; a temperature sensor; a 10-channel, 12-bit analog-to-digital converter; and an 8-bit microcontroller with a 16-bit hardware multiplier and a 40-bit accumulator. Serial and parallel interfaces allow digital communication with a host system. Fabricated in a standard 0.35 mm digital CMOS process, the die occupies 3:8mm 4:1 mm, operates from a nominal supply voltage of 3 V, and draws 16 mA when fully powered �850 mA standby current). To facilitate testing of the prototype, extra pads are bonded out to package pins. The chips are

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the effects of device noise. Simulation of the feedback loop filters with SpectreRF provides the statistics of the device noise. A discrete time filter is used to generate noise with similar power spectral density (PSD) during the behavioral simulation. A second order converter is used to demonstrate the methodology and the simulation results are presented. Our approach does not make assumptions about the device and quantization noise adding linearly and takes into account their interaction. It is numerically efficient, as the behavioral simulation does not require significantly higher computational effort than in the case that device noise is not included. The same approach can be applied to continuous time converters. Originally written in August 1999, was first published in April 2003. Last updated on May 12, 2006. You can find the most recent version at www.designers-guide.org. Permission to make copies, either paper or electronic, of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage and that the copies are complete and unmodified. To distribute otherwise, to publish, to post on servers, or to distribute to lists, requires prior written permission.

Copyright © 2008, by the author(s).

: An operational amplifier designed with 0.35um CMOS technology is presented. All the transistors are realized with minimum or near-minimum channel length. As the short channel length causes performance degradation, a proper operational amplifier structure is selected to compensate the performance degradation. The op amp is designed to meet the requirement of high-speed high-resolution sigma delta modulators. It has a folded-cascode first stage and a class-A output stage. It features a DC gain of 78dB, an openloop unity-gain frequency of 266MHZ, a slew rate of 650V/us, and consumes 10.2mW from a +/-1.5V power supply. High level simulation is used to evaluate the OTA performance in sigma delta modulators. 1. INTRODUCTION The fast development of CMOS process technique makes it possible to integrate more and more functions into a single Digital-signal-Processing chip. However, the physical signal (which is analog) still needs an interface to be handled by DSP. A/D and D/A converters are...

This paper presents a polarity alternating feedback (PAF) comparator with a high sampling speed in the range of two to six GS/s with a low power consumption of 140 mW including output bu#ers. Using the PAF comparator, we have designed and fabricated a secondorder ##ADC that has the lowest power consumption Manuscript received July 22, 1998.