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Software Transactional Memory
, 1995
"... As we learn from the literature, flexibility in choosing synchronization operations greatly simplifies the task of designing highly concurrent programs. Unfortunately, existing hardware is inflexible and is at best on the level of a Load Linked/Store Conditional operation on a single word. Building ..."
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Cited by 565 (14 self)
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As we learn from the literature, flexibility in choosing synchronization operations greatly simplifies the task of designing highly concurrent programs. Unfortunately, existing hardware is inflexible and is at best on the level of a Load Linked/Store Conditional operation on a single word. Building on the hardware based transactional synchronization methodology of Herlihy and Moss, we offer software transactional memory (STM), a novel software method for supporting flexible transactional programming of synchronization operations. STM is nonblocking, and can be implemented on existing machines using only a Load Linked/Store Conditional operation. We use STM to provide a general highly concurrent method for translating sequential object implementations to lockfree ones based on implementing a kword compare&swap STMtransaction. Empirical evidence collected on simulated multiprocessor architectures shows that the our method always outperforms all the lockfree translation methods in ...
Universal Operations: Unary Versus Binary
, 1996
"... 1 1 Introduction 2 2 Related Work 5 3 Preliminaries 7 3.1 The Asynchronous SharedMemory Model : : : : : : : : : : : : : : : : : : : 7 3.2 Sensitivity : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8 4 The Left/Right Algorithm 11 4.1 The General Scheme : : : : : : : ..."
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Cited by 28 (2 self)
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1 1 Introduction 2 2 Related Work 5 3 Preliminaries 7 3.1 The Asynchronous SharedMemory Model : : : : : : : : : : : : : : : : : : : 7 3.2 Sensitivity : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8 4 The Left/Right Algorithm 11 4.1 The General Scheme : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 11 4.2 The Left/Right Algorithm : : : : : : : : : : : : : : : : : : : : : : : : : : : : 13 4.2.1 Overview : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 13 4.2.2 The code : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 14 4.2.3 Correctness of the Algorithm : : : : : : : : : : : : : : : : : : : : : : 16 4.2.4 Analysis of the Algorithm : : : : : : : : : : : : : : : : : : : : : : : : 18 4.3 Inherently Asymmetric Data Structures : : : : : : : : : : : : : : : : : : : : 21 5 The Decision Algorithm 23 5.1 Monotone Paths : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 23 5.1.1 One Phase :...
The QueueRead QueueWrite Asynchronous PRAM Model
 EuroPar'96 Parallel Processing, Lecture Notes in Computer Science
, 1998
"... This paper presents results for the queueread, queuewrite asynchronous parallel random access machine (qrqw asynchronous pram) model, which is the asynchronous variant of the qrqw pram model. The qrqw pram family of models, which was introduced earlier by the authors, permit concurrent reading ..."
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Cited by 24 (8 self)
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This paper presents results for the queueread, queuewrite asynchronous parallel random access machine (qrqw asynchronous pram) model, which is the asynchronous variant of the qrqw pram model. The qrqw pram family of models, which was introduced earlier by the authors, permit concurrent reading and writing to shared memory locations, but each memory location is viewed as having a queue which can service at most one request at a time. In the basic qrqw pram model each processor executes a series of reads to shared memory locations, a series of local computation steps, and a series of writes to shared memory locations, and then synchronizes with all other processors; thus this can be viewed as a bulksynchronous model. In contrast, in the qrqw asynchronous pram model discussed in this paper, there is no imposed bulksynchronization between processors, and each processor proceeds at its own pace. Thus, the qrqw asynchronous pram serves as a better model for designing and analyz...
Improved implementations of binary universal operations
 J. ACM
, 2001
"... We present an algorithm for implementing binary operations (of any type) from unary loadlinked (LL) and storeconditional (SC) operations. The performance of the algorithm is evaluated according to its sensitivity, measuring the distance between operations in the graph induced by conflicts, which gu ..."
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Cited by 9 (7 self)
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We present an algorithm for implementing binary operations (of any type) from unary loadlinked (LL) and storeconditional (SC) operations. The performance of the algorithm is evaluated according to its sensitivity, measuring the distance between operations in the graph induced by conflicts, which guarantees that they do not influence the step complexity of each other. The sensitivity of our implementation is O(log\Lambda n), where n is the number of processors in the system. That is, operations that are \Omega (log\Lambda n) apart in the graph induced by conflicts do not delay each other. Constant sensitivity is achieved for operations used to implement heaps and arraybased linked lists.
Universal Operations: Unary versus Binary (Extended Abstract)
"... ) Hagit Attiya and Eyal Dagan Department of Computer Science The Technion Haifa 32000, Israel Abstract An algorithm for implementing binary operations (of any type) from unary loadlinked (LL) and storeconditional (SC ) operations is presented. The performance of the algorithm is measured by its s ..."
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) Hagit Attiya and Eyal Dagan Department of Computer Science The Technion Haifa 32000, Israel Abstract An algorithm for implementing binary operations (of any type) from unary loadlinked (LL) and storeconditional (SC ) operations is presented. The performance of the algorithm is measured by its sensitivity, i.e., how far (in terms of distances in the graph induced by the contention among overlapping operations) should operations be in order not to influence the step complexity of each other. The sensitivity of this implementation is at most O(log n), where n is the number of the processors in the system. That is, operations that are at least O(log n) apart in the contention graph do not delay each other. In some cases, where the data sets of the operations are restricted, e.g., in operations used to implement linked lists and heaps, the sensitivity is O(1). We also prove a negative result. We show that there is a problem which can be solved in O(1) steps using binary LL/SC o...