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Abstract state machines capture parallel algorithms
- ACM Transactions on Computational Logic
, 2003
"... Abstract We give an axiomatic description of parallel, synchronous algorithms. Our main result is that every such algorithm can be simulated, step for step, by an abstract state machine with a background that provides for multisets. \Lambda ..."
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Cited by 48 (19 self)
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Abstract We give an axiomatic description of parallel, synchronous algorithms. Our main result is that every such algorithm can be simulated, step for step, by an abstract state machine with a background that provides for multisets. \Lambda
Matrix Chain Ordering in Polylog Time with n/lg n Processors
- Proceedings of the 8th Annual IEEE International Parallel Processing Symposium (IPPS), Cancun
, 1993
"... This paper gives a O(lg 4 n) time and n=lg n processor algorithm for solving the matrix chain ordering problem and for finding optimal triangulations of a convex polygon on the Common CRCW PRAM model. This algorithm works by finding shortest paths in special digraphs modeling dynamic programming t ..."
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Cited by 5 (4 self)
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This paper gives a O(lg 4 n) time and n=lg n processor algorithm for solving the matrix chain ordering problem and for finding optimal triangulations of a convex polygon on the Common CRCW PRAM model. This algorithm works by finding shortest paths in special digraphs modeling dynamic programming tables. These shortest paths are found cheaply using new and efficient techniques for exploiting monotonic problem constraints. 1 Introduction Recently, much research has gone into designing efficient parallel algorithms for problems with elementary serial dynamic programming solutions. These problems include string editing [1, 3], context free grammar recognition [22, 21], and optimal tree building [2, 19]. Polylog time parallel algorithms for solving these problems use new approaches since straightforward parallelization of sequential dynamic programming algorithms produces very slow (linear-time) parallel algorithms. Many efficient parallel algorithms designed to date rely on monotonicity...
Planar Stage Graphs: Characterizations And Applications
, 1995
"... We consider combinatorial and algorithmic aspects of the well-known paradigm "killing two birds with one stone". We define a stage graph as follows: vertices are the points from a planar point set, and fu; vg is an edge if and only if the (infinite, straight) line segment joining u to v intersects a ..."
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Cited by 3 (3 self)
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We consider combinatorial and algorithmic aspects of the well-known paradigm "killing two birds with one stone". We define a stage graph as follows: vertices are the points from a planar point set, and fu; vg is an edge if and only if the (infinite, straight) line segment joining u to v intersects a given line segment, called a stage. We show that a graph is a stage graph if and only if it is a permutation graph. The characterization results in a compact linear space representation of stage graphs. This has been exploited for designing improved algorithms for matching in permutation graphs, two processor task scheduling for dependency graphs known to be permutation graphs, and dominance related problems for planar point sets. 1980 Mathematics Subject Classification: 68R10, 68U05 CR Categories: F.2.2 Key Words and Phrases: Algorithms and Data Structures, Dominance, Matching, Processor Scheduling, Permutational Graphs, Coding of Orders, 2-dimensional Partial Orders, Stage Graphs. Car...
An Efficient Parallel Algorithm for the General Planar Monotone Circuit Value Problem
, 1996
"... . A planar monotone circuit (PMC) is a Boolean circuit that can be embedded in the plane and that contains only AND and OR gates. Goldschlager, Cook & Dymond and others have developed NC 2 algorithms to evaluate a special layered form of a PMC. These algorithms require a large number of processors ..."
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Cited by 3 (0 self)
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. A planar monotone circuit (PMC) is a Boolean circuit that can be embedded in the plane and that contains only AND and OR gates. Goldschlager, Cook & Dymond and others have developed NC 2 algorithms to evaluate a special layered form of a PMC. These algorithms require a large number of processors(\Omega\Gamma n 6 ), where n is the size of the input circuit). Yang, and more recently, Delcher & Kosaraju have given NC algorithms for the general planar monotone circuit value problem. These algorithms use at least as many processors as the algorithms for the layered case. This paper gives an efficient parallel algorithm that evaluates a general PMC of size n in polylog time using only a linear number of processors on an EREW PRAM. This parallel algorithm is the best possible to within a polylog factor, and is a substantial improvement over the earlier algorithms for the problem. The algorithm uses several novel techniques to perform the evaluation, including the use of the dual of the...
An Efficient Parallel Algorithm for the Layered Planar Monotone Circuit Value Problem
- Proc. 1st European Symp. on Algorithms, Springer-Verlag, LNCS 726
, 1993
"... A planar monotone circuit (PMC) is a Boolean circuit that can be embedded in the plane and that contains only AND and OR gates. A layered PMC is a PMC in which all input nodes are in the external face, and the gates can be assigned to layers in such a way that every wire goes between gates in suc ..."
Abstract
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A planar monotone circuit (PMC) is a Boolean circuit that can be embedded in the plane and that contains only AND and OR gates. A layered PMC is a PMC in which all input nodes are in the external face, and the gates can be assigned to layers in such a way that every wire goes between gates in successive layers. Goldschlager, Cook & Dymond and others have developed NC 2 algorithms to evaluate a layered PMC when the output node is in the same face as the input nodes. These algorithms require a large number of processors(\Omega\Gamma n 6 ), where n is the size of the input circuit). In this paper, we give an efficient parallel algorithm that evaluates a layered PMC of size n in O(log 2 n) time using only a linear number of processors on an EREW PRAM. Our parallel algorithm is the best possible to within a polylog factor, and is a substantial improvement over the earlier algorithms for the problem. This work was supported in part by Texas Advanced Research Projects Grant ...

