With the increasing complexity of manufacturing processes and the shrinking of device geometries, the performance metrics of integrated circuits (ICs) are becoming increasingly sensitive to random fluctuations in the manufacturing process. We propose a diagnosis methodology that can be used to infer the cause(s) of variations in performance of analog ICs. The methodology consists of (a) a device parameter computation technique which is used to compute the device parameters of an IC from measurements made on it and (b) a cause-effect analysis module that is used to compute the cause of the variation in performance metrics of a given set of ICs. Simulation results to demonstrate the effectiveness of the technique are presented. 1.

This paper describesa new CAD algorithm which performsautomatic test pattern generation (ATPG) for a general class of analog systems, namely those circuits which can be efficiently modeled as an additive combination of user-defined basis functions. The algorithm is based on the statistical technique of I-optimal experimental design, in which test vectors are chosen to be maximally independent so that circuit performance will be characterized as accurately as possible in the presence of measurement noise and model inaccuracies. This technique allows analog systems to be characterized more accurately and more efficiently, thereby significantly reducing system test time and hence total manufacturing cost. 1 Introduction The complexity of electronic systems being designed today is increasing in many dimensions: on one hand, the number of components is growing constantly; on the other, several radically different functions must be integrated. For example, in the exploding personal communi...

This paper presents a new low-cost fault diagnosis technique based on Built-in Self Test (BIST). The method enables rapid and accurate identification of weak spots in a design and potential problems in the manufacturing process, thereby leading to a significant reduction in time-tomarket. Fault diagnosis is accelerated with available onchip BIST which can generate low-cost signatures (performance parameters). Imperfect signatures due to limited onchip resources and accuracy are compensated in two ways. Supplemental signatures are obtained from a re-configured Device Under Test (DUT) by parameter tuning, leading to improvements in diagnosability. Secondly, diagnosis accuracy is significantly improved by using an ensemble method which has been widely used in data mining. The technique can be used to identify single as well as multiple faults, and can also be used to facilitate a self-repair mechanism by accurately identifying the source of errors. Simulation results are presented to validate the technique. 1