Results 1  10
of
39
Design and analysis of dynamic Huffman codes
 Journal of the ACM
, 1987
"... Abstract. A new onepass algorithm for constructing dynamic Huffman codes is introduced and analyzed. We also analyze the onepass algorithm due to Failer, Gallager, and Knuth. In each algorithm, both the sender and the receiver maintain equivalent dynamically varying Huffman trees, and the coding i ..."
Abstract

Cited by 96 (3 self)
 Add to MetaCart
Abstract. A new onepass algorithm for constructing dynamic Huffman codes is introduced and analyzed. We also analyze the onepass algorithm due to Failer, Gallager, and Knuth. In each algorithm, both the sender and the receiver maintain equivalent dynamically varying Huffman trees, and the coding is done in real time. We show that the number of bits used by the new algorithm to encode a message containing t letters is < t bits more than that used by the conventional twopass Huffman scheme, independent of the alphabet size. This is best possible in the worst case, for any onepass Huffman method. Tight upper and lower bounds are derived. Empirical tests show that the encodings produced by the new algorithm are shorter than those of the other onepass algorithm and, except for long messages, are shorter than those of the twopass method. The new algorithm is well suited for online encoding/decoding in data networks and for file compression.
Code Compression for Embedded Systems
, 1998
"... Memory is one of the most restrictedresources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressedcode CPU, acache miss triggers the decompression of a main memory block, before it gets transferred to the cache. Because the code must bed ..."
Abstract

Cited by 63 (2 self)
 Add to MetaCart
(Show Context)
Memory is one of the most restrictedresources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressedcode CPU, acache miss triggers the decompression of a main memory block, before it gets transferred to the cache. Because the code must bedecompressible starting from any point #or at least at cache block boundaries#, most #leorientedcompression techniques cannot be used. We propose two algorithms to compress code in a spacee#cient and simple to decompress way, one which is independent of the instruction set and another which depends on the instruction set. We perform experiments on two instruction sets, a typical RISC #MIPS# and a typical CISC #x86# and compare our results to existing #leorientedcompression algorithms. 1 Introduction Manyembedded computing systems are space and cost sensitive. As a result, available memory is limited, posing serious constraints on program size. We are studying ways of reducing the size of...
Practical Implementations of Arithmetic Coding
 IN IMAGE AND TEXT
, 1992
"... We provide a tutorial on arithmetic coding, showing how it provides nearly optimal data compression and how it can be matched with almost any probabilistic model. We indicate the main disadvantage of arithmetic coding, its slowness, and give the basis of a fast, spaceefficient, approximate arithmet ..."
Abstract

Cited by 35 (6 self)
 Add to MetaCart
We provide a tutorial on arithmetic coding, showing how it provides nearly optimal data compression and how it can be matched with almost any probabilistic model. We indicate the main disadvantage of arithmetic coding, its slowness, and give the basis of a fast, spaceefficient, approximate arithmetic coder with only minimal loss of compression efficiency. Our coder is based on the replacement of arithmetic by table lookups coupled with a new deterministic probability estimation scheme.
Efficient decoding of prefix codes
 COMMUNICATIONS OF THE ACM
, 1990
"... We discuss representations of prefix codes and the corresponding storage space and decoding time requirements. We assume that a dictionary of words to be encoded has been defined and that a prefix code appropriate to the dictionary has been constructed. The encoding operation becomes simple given th ..."
Abstract

Cited by 32 (0 self)
 Add to MetaCart
We discuss representations of prefix codes and the corresponding storage space and decoding time requirements. We assume that a dictionary of words to be encoded has been defined and that a prefix code appropriate to the dictionary has been constructed. The encoding operation becomes simple given these assumptions and given an appropriate parsing strategy, therefore we concentrate on decoding. The application which led us to this work constrains the use of internal memory during the decode operation. As a result, we seek a method of decoding which has a small memory requirement.
A HighSpeed Asynchronous Decompression Circuit for Embedded Processors
"... This paper describes the architecture and implementation of a highspeed decompression engine for embedded processors. The engine is targeted to processors where embedded programs are stored incompressed form, and decompressed at runtime during instruction cache re ll. The decompression engine uses ..."
Abstract

Cited by 26 (4 self)
 Add to MetaCart
This paper describes the architecture and implementation of a highspeed decompression engine for embedded processors. The engine is targeted to processors where embedded programs are stored incompressed form, and decompressed at runtime during instruction cache re ll. The decompression engine uses a unique asynchronous variable decompression rate architecture to process Huffmanencoded instructions. The resulting circuit is significantly smaller than comparable synchronous decoders, yet has a higher throughput rate than almost all existing designs. The 0.8 layout is all fullcustom and contains predominantly dynamic domino logic. The toplevel control, as well as several small state machines, are implemented using asynchronous logic. The design operates without a usersupplied clock. Simulations using Lsim show average throughput of 32 bits/45 ns on the output side, corresponding to about 480 Mbit/sec on the input side. The chip has been manufactured by MOSIS; tests show that the asynchronous implementation operates correctly, with an average throughput exceeding simulations: 32 bits/39 ns on the output side, corresponding to about 560 Mbit/sec on the input side. This speed isacceptable for our application. The area of the design (excluding the padframe overhead) is only 0.75 mm². The design is the first fabricated chip for an instruction decompression unit for embedded processors.
Energyefficient indexing for information dissemination in wireless systems
 ACM JOURNAL OF MOBILE NETWORKS AND APPLICATIONS
, 1996
"... We consider the application of high volume information dissemination in broadcast based mobile environments. Since current mobile units accessing broadcast information have limited battery capacity, the problem of quick and energyefficient access to data becomes particularly relevant as the number ..."
Abstract

Cited by 23 (0 self)
 Add to MetaCart
We consider the application of high volume information dissemination in broadcast based mobile environments. Since current mobile units accessing broadcast information have limited battery capacity, the problem of quick and energyefficient access to data becomes particularly relevant as the number and sizes of information units increases. We propose several randomized and Huffmanencoding based indexing schemes that are sensitive to data popularity patterns to structure data transmission on the wireless medium, so that the average energy consumption of mobile units is minimized while trying to access desired data. We then propose an algorithm for PCS units to tune into desired data independent of the actual transmission scheme being used. We also empirically study the proposed schemes and propose different transmission modes for the base station to dynamically adapt to changes in the number of data files to be broadcasted, the available bandwidth and the accuracy of data popularity patterns.
Joint SourceChannel Decoding Of VariableLength Encoded Sources With Applications To Image Transmission
, 2000
"... Shannon's sourcechannel separation theorem holds only under asymptotic conditions, where both source and channel codes are allowed infinite length and complexity, which is not possible in practice. This observation has led to the increasing popularity of joint sourcechannel encoding and decod ..."
Abstract

Cited by 17 (1 self)
 Add to MetaCart
Shannon's sourcechannel separation theorem holds only under asymptotic conditions, where both source and channel codes are allowed infinite length and complexity, which is not possible in practice. This observation has led to the increasing popularity of joint sourcechannel encoding and decoding schemes as viable alternatives for achieving reliable communication of signals across noisy channels. Joint sourcechannel encoders (JSCE) aim at designing the source and channel encoder of a system in some joint sense, while joint sourcechannel decoders (JSCD) concentrate on the design of the decoder. JSCD schemes have been
Dynamic Huffman Coding
, 1989
"... . We present a Pascal implementation of the onepass algorithm for constructing dynamic Huffman codes that is described and analyzed in a companion paper [Vitter, 1987]. The program runs in real time ..."
Abstract

Cited by 13 (2 self)
 Add to MetaCart
. We present a Pascal implementation of the onepass algorithm for constructing dynamic Huffman codes that is described and analyzed in a companion paper [Vitter, 1987]. The program runs in real time
Decomposition of logic functions for minimum transition activity
 In Proceedings of the 1994 International Workshop on Low Power Design
, 1994
"... In this age of portable electronic systems, the problem of logic synthesis for low power has acquired great importance. The most popular approach has been to target the widelyaccepted twophase paradigm of technologyindependent optimization and technology mapping for power minimization. Before mapp ..."
Abstract

Cited by 13 (0 self)
 Add to MetaCart
(Show Context)
In this age of portable electronic systems, the problem of logic synthesis for low power has acquired great importance. The most popular approach has been to target the widelyaccepted twophase paradigm of technologyindependent optimization and technology mapping for power minimization. Before mapping, each function of a multilevel network is decomposed into twoinput gates. How this decomposition is done can have a signi cant impact on the power dissipation of the nal implementation. The problem of decomposition for low power was recently addressed by Pedram et al. [11]. However, they ignore the power consumption due to glitches, which can be a sizeable fraction of the total power [3]. In this paper, we show howto obtain a transitionoptimum binary tree decomposition (i.e., the one which has minimum number of transitions in the worst case, including those due to glitches) for some speci c functions (AND, OR, and EXOR) for zero gate delay model. For a nonzero gate delay model, we present conditions under which our algorithm yields an optimum solution for such functions. We propose a straightforward extension of this algorithm for arbitrary functions and Boolean networks. Experimental results on a set of standard combinational benchmarks indicate that on average, our algorithm generates networks (using twoinput gates) that have 16 % fewer transitions in the worst case than the networks generated by a simpleminded twoinput technologydecomposition algorithm implementedinsis [8], a widely used logic synthesis system. 1
Translationbased steganography
 In Proceedings of Information Hiding Workshop (IH 2005
, 2005
"... This paper investigates systems that steganographically embed information in the “noise ” created by automatic translation of natural language documents. The main thrust of the work focuses on two problems generation of plausible steganographic texts, and avoiding transmission of the original sourc ..."
Abstract

Cited by 10 (4 self)
 Add to MetaCart
This paper investigates systems that steganographically embed information in the “noise ” created by automatic translation of natural language documents. The main thrust of the work focuses on two problems generation of plausible steganographic texts, and avoiding transmission of the original source for stego objects. Because the inherent redundancy of natural language creates plenty of room for variation in translation, machine translation is ideal for steganographic applications. We describe the design and implementation of a scheme for hiding information in translated natural language text and present experimental results using the implemented system. While the initial work in this vein required the presence of both the source and the translation, the system detailed in this paper requires only the translated text for recovering the hidden message, increasing security and improving resource usage. These improvements occur not only because the source text is no longer available to the adversary, but also because a broader repertoire of defenses (such as mixing human and machine translation) can now be used. ∗ Preliminary and shorter versions of this work appeared in [21, 38]. 1 1