The switch-level model represents a digital metal-oxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new network state. This analysis supports the same class of networks as the switch-level simulator MOSSIM II and provides the same functionality, including the handling of bidirectional e ects and indeterminate (X) logic values. In the worst case, the analysis of an n node network can yield a set of formulas containing a total of O(n 3) operations. However, all but a limited set of dense, pass-transistor networks give formulas with O(n) total operations. The analysis can serve as the basis of e cient programs for a variety oflogic design tasks, including: logic simulation (on both conventional and special purpose computers), fault simulation, test generation, and symbolic veri cation.

The cosmos simulator provides fast and accurate switch-level modeling of mos digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer anamos, captures all aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values. The lgcc program translates the Boolean representation into a set of machine language evaluation procedures and initialized data structures. These procedures and data structures are compiled along with code implementing the simulation kernel and user interface to produce the simulation program. The simulation program runs an order of magnitude faster than our previous simulator mossim ii.

A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean equations. For the class of networks that arise when analyzing digital metal-oxide semiconductor (MOS) circuits, a simple pivot selection rule guarantees that most s switch networks encountered in practice can be solved with O(s) operations. When represented by a directed acyclic graph, the set of Boolean formulas generated by the analysis has total size bounded by the number of operations required by the Gaussian elimination. This paper presents the mathematical basis for systems of Boolean equations, their solution by Gaussian elimination, and data structures and algorithms for representing and manipulating Boolean formulas.

We implement and experiment with techniques for the functional simulation of very large digital systems. We consider techniques that are a hybrid of classical compiled code simulation and recent branching program based simulation in order to resolve memory performance problems inherentto BDD based cycle simulation. Specifically, predefined functional units ("macros") are extracted from the circuit and evaluated directly instead of building BDDs for them. The functionality of those macros, such as multipliers, filters, etc., can in turn be verifjed by simulation of their gate-level implementations respectively or by formal verification techniques. Our results demonstrate that this approach leads to considerably faster simulation. 1 Introduction Design verification is a crucial step in the process of designing a digital system. The complexity of design has increased dramatically over the past few years, and this trend continues unabated in the deep sub-micron era. Consequently ,a very large e...

. We investigate the question whether and to what extend the solution of central tasks of digital logic circuit design of a given Boolean function f benefits from a representation of f in terms of certain restricted decision graphs or branching programs. Introduction One of the fundamental problems in computer-aided circuit design is the task of representing logic functions. Although, in principle, any valid representation is allowed, some representations may be preferred because they are -- more efficient in memory, -- more efficient to manipulate, or -- more indicative of the complexity of the final implementation. The search of an optimal trade--off between these competing objectives -- succinct representation of Boolean functions and feasible manipulation algorithms -- is a central theme of logic synthesis. The most fundamental concept in the description of logic functions is that of the truth table. Truth tables define a function by listing the output value for each possible inp...

We describe a method for generating logic simulation code which correctly responds to any number of undefined logic values at the code inputs. The method is based on our development of the Ordered Ternary Decision Diagram, itself based on Kleenean ternary logic, which explicitly and correctly manages the unknown logic value `U' in addition to the `1' and `0' of conventional OBDDs. We describe the OTDD and how to implement its reduction, application, and restriction operations. This method avoids expensive technology mapping, producing highly efficient `U'-correct compiled logic simulation code in seconds rather than in hours. Our experiments toward confirming the validity of the method are reported.