Results 1 - 10 of 20

Kestrel: A Programmable Array for Sequence Analysis

by Jeffrey D. Hirschberg, David M. Dahle, Kevin Karplus, Don Speck, Richard Hughey , 1998
"... Kestrel is a programmable linear array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, a multiplier and efficient communication using shared registers. This paper describes Kestrel’s functional units in de ..."
Abstract - Cited by 27 (10 self) - Add to MetaCart
Kestrel is a programmable linear array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, a multiplier and efficient communication using shared registers. This paper describes Kestrel’s functional units in detail, and examines each of their effects on system performance. With functional prototype chips completed, we will assemble a full single-board Kestrel array, with 512 processing elements on eight chips, in early 1998.
(Show Context)

B-SYS: A 470-Processor Programmable Systolic Array

by Richard Hughey, Daniel P. Lopresti - in Proc. Int. Conf. Parallel Processing , 1991
"... This paper presents an architecture for programmable systolic arrays that provides simple and efficient systolic communication. The Brown Systolic Array is a linear implementation of this Systolic Shared Register architecture; a working 470-processor prototype system performs 108 MOPS. A 32-chip, 15 ..."
Abstract - Cited by 19 (9 self) - Add to MetaCart
This paper presents an architecture for programmable systolic arrays that provides simple and efficient systolic communication. The Brown Systolic Array is a linear implementation of this Systolic Shared Register architecture; a working 470-processor prototype system performs 108 MOPS. A 32-chip, 1504-processor implementation could provide 5 GOPS of systolic co-processing power on a single board. Keywords: systolic array, parallel processing, VLSI, SIMD, sequence comparison. Introduction The systolic array is perhaps the most significant architectural development inspired by the revolution in VLSI fabrication technology. By pumping data through a regular network of hundreds or thousands of simple processing elements, computationally intensive problems can be solved many times faster on systolic arrays than on traditional machines. Since the introduction of the systolic paradigm, systolic co-processors have been proposed to solve a wide variety of problems. However, new VLSI single-pu...
(Show Context)

A Special-Purpose Processor for Gene Sequence Analysis

by Barry Fagin, J. Gill Watt, Robert Gross - Comptuer Applications in the Biosciences , 1992
"... Advances in computational biology have occurred primarily in the areas of software and algorithm development; new designs of hardware to support biological computing are extremely scarce. This is due, we believe, to the presence of a non-trivial knowledge gap between molecular biologists and compute ..."
Abstract - Cited by 11 (1 self) - Add to MetaCart
Advances in computational biology have occurred primarily in the areas of software and algorithm development; new designs of hardware to support biological computing are extremely scarce. This is due, we believe, to the presence of a non-trivial knowledge gap between molecular biologists and computer designers. The existence of this gap is unfortunate, as it has long been known that for certain problems, special-purpose computers can achieve significant cost/performance gains over general purpose machines. We describe one such computer here: a custom accelerator for gene sequence analysis. The accelerator implements a version of the Needleman-Wunsch algorithm for nucleotide sequence alignment. Sequence lengths are constrained only by available memory; the product of sequence lengths in the current implementation can be up to 2 22 . The machine is implemented as two NuBus boards connected to a Mac II f/x, using a mixture of TTL and FPGA technology clocked at 10 MHz. The boards are compl...

Dedicated Hardware for Biological Sequence Comparison

by Dominique Lavenier - Journal of Universal Computer Science , 1996
"... Abstract: Biological sequence comparison is a time consuming task on a Von Neuman computer. The addition of dedicated hardware for parallelizing the comparison algorithms results in a reduction of several orders of magnitude in the execution time. This paper presents and compares di erent dedicated ..."
Abstract - Cited by 10 (2 self) - Add to MetaCart
Abstract: Biological sequence comparison is a time consuming task on a Von Neuman computer. The addition of dedicated hardware for parallelizing the comparison algorithms results in a reduction of several orders of magnitude in the execution time. This paper presents and compares di erent dedicated approaches, based on the parallelization of the algorithms on linear arrays of processors.
(Show Context)

Relacs for systolic programming

by F Raimbault, D Lavenier - In Int’l Conf. on Application-Specific Array Processors , 1993
"... ..."
Abstract - Cited by 6 (5 self) - Add to MetaCart
Abstract not found

Massively Parallel Biosequence Analysis

by Richard Hughey , 1993
"... Massive parallelism is required for the analysis of the rapidly growing biosequence databases. First, this paper compares and benchmarks methods for dynamic programming sequence analysis on several parallel platforms. Next, a new hidden Markov model method and its implementation on several paralle ..."
Abstract - Cited by 6 (2 self) - Add to MetaCart
Massive parallelism is required for the analysis of the rapidly growing biosequence databases. First, this paper compares and benchmarks methods for dynamic programming sequence analysis on several parallel platforms. Next, a new hidden Markov model method and its implementation on several parallel machines is discussed. Finally, the results of a series of experiments using this massively parallel implementation are described.

A Systolizing Compiler

by Michael Barnett - Distributed Computing , 1992
"... We present an automatic scheme to generate programs for distributed-memory multiprocessors. We begin with a source program that contains no references to concurrency or communication. The source program corresponds to a systolic array: as such, it is a nested loop program with regular data dependenc ..."
Abstract - Cited by 5 (0 self) - Add to MetaCart
We present an automatic scheme to generate programs for distributed-memory multiprocessors. We begin with a source program that contains no references to concurrency or communication. The source program corresponds to a systolic array: as such, it is a nested loop program with regular data dependences. The loop bounds may be any linear function of enclosing indices and of variables representing the problem size. The target programs are in an abstract syntax that can be translated to any distributed programming language with asynchronous parallelism and rendezvous communication; so far, a translator to occam 2 has been completed. The scheme is based on a formal theory of linear transformations and has been formally verified. The complexity of the scheme is independent of the problem size. It has been implemented. In contrast to other compilation methods, the scheme derives every aspect of the distributed program, including i/o and communication directives. It represents the first comple...
(Show Context)

Fault-Tolerant and Efficient Parallel Computation

by Alexander Allister Shvartsman , 1992
"... Recent advances in computer technology made parallel machines a reality. Massively parallel systems use many general-purpose, inexpensive processing elements to attain computation speed-ups comparable to or better than those achieved by expensive, specialized machines with a small number of fast pro ..."
Abstract - Cited by 3 (1 self) - Add to MetaCart
Recent advances in computer technology made parallel machines a reality. Massively parallel systems use many general-purpose, inexpensive processing elements to attain computation speed-ups comparable to or better than those achieved by expensive, specialized machines with a small number of fast processors. In such setting, however, one would expect to see an increased number of processor failures attributable to hardware or software. This may eliminate the potential advantage of parallel computation. We believe that this presents a reliability bottleneck that is among fundamental problems in parallel computation.

Parallel Architecture for Flexible Approximate Text Searching

by Panagiotis D. Michailidis, Konstantinos G. Margaritis - CD-ROM Proc. Seventh WSEAS Int’l Multiconf. Circuits, Systems, Comm. and Computers (WSEAS-CSCC 2003 , 2003
"... Abstract:- This paper presents a processor array design for flexible approximate string matching. Initially, a sequential algorithm is discussed which consists of two phases, i.e. preprocessing and searching. Then, starting from the computational schedule of the searching phase a parallel architectu ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
Abstract:- This paper presents a processor array design for flexible approximate string matching. Initially, a sequential algorithm is discussed which consists of two phases, i.e. preprocessing and searching. Then, starting from the computational schedule of the searching phase a parallel architecture is derived. Further, the preprocessing phase is also accomodated onto the same architecture. Key-Words:- Approximate string matching; processor arrays; parallel architecture 1
(Show Context)

Comments Clustering Techniques on Transformation Systems

by Peer Bartels, Peer Bartels , 2007
"... The common use of computer systems or application programs over a long period of time can result in quite large and complex systems which may develop to the state where they typically resist further modification and evolution. Such systems are also known as Legacy Systems [124]. These systems usuall ..."
Abstract - Add to MetaCart
The common use of computer systems or application programs over a long period of time can result in quite large and complex systems which may develop to the state where they typically resist further modification and evolution. Such systems are also known as Legacy Systems [124]. These systems usually form the backbone of information flow within an organisation or company and are normally mission critical. If one of these systems stops working the business will generally grind to a halt. Legacy system migration is focused on the development of a target system which retains the functionality and, importantly, data of the original legacy system [124]. However, Legacy systems can be maintained and adapted easily to meet future business requirements. The idea is not new, as some approaches already do exist which allow the migration of such systems to new platforms and architectures which also provide tools and scientific methods to support such a strategy. One approach is the ”‘FermaT Transformation System” ’ developed by Martin Ward at the University of Oxford, which has demonstrated that legacy systems can be transformed securely to a high level programming language such as C or Cobol [6]. The invented environment is based on a mathematical proven code transformations and is called ”FermaT Transformation Engine”. It uses an intermediate