In the context of developing a compiler for a Alpha, a functional dataparallel language based on systems of affine recurrence equations (SAREs), we address the problem of transforming scheduled single-assignment code to multiple assignment code. We show how the polyhedral model allows us to statically compute the lifetimes of program variables, and thus enables us to derive necessary and sufficient conditions for reusing memory. 1. Introduction The methodology of automatic systolic array synthesis from Systems of Affine Recurrence Equations (SAREs) has a close bearing on parallelizing compilers and on efficient implementation of functional languages. To study this relationship, we are currently developing a compiler for Alpha [9], a functional, data parallel language based on SAREs defined over polyhedral index domains. The language semantics directly lead to sequential code based on demand driven evaluation. However, the resulting context switches can be avoided if the program is tra...

Tiling is a common compiler optimization, used for adjusting the parallelism granularity or for enhancing locality. For the case of a 2-dimensional iteration space (domain) tiled with oblique tiles, we address the problem of determining the tile size that minimizes the total execution time on a distributed memory parallel machine. We restrict our attention to uniform dependency computations where one of the tile boundaries is nevertheless parallel to the domain boundaries, in the interest of good load balance. Our solution is obtained by formulating and resolving a discrete nonlinear optimization problem. Experimental running times on an Intel Paragon and an IBM SP2 compare well with our analytical predictions. 1 Introduction Iteration space tiling [Wol87, IT88] is a technique used by parallelizing compilers to improve data locality, and to increase the computation to communication ratio by varying the granularity of the computation. It may also be used for hand tuning the performance...

In pipelined parallel computations the inner loops are often implemented in a block fashion. In such programs, an important compiler optimization involves the need to statically determine the grain size. This paper presents extensions and experimental validation of the previous results of Andonov and Rajopadhye on optimal grain size determination. Keywords: iteration space tiling, coarse grain pipelining, SPMD programs, distributed memory machines, communicationcomputation overlap, nonlinear optimization, supernode partitioning, automatic parallelization, macro-systolic arrays. 1. Introduction Tiling the iteration space [7, 12, 15] is a common method for improving the performance of parallel loop programs executed in SPMD (Single Program Multiple Data) fashion on a DMM (distributed memory machine). It may be used as a technique in parallelizing compilers (see [6, 11] where it is also called coarse-grain pipelining) as well as in performance tuning of parallel codes by hand (see also ...

: Iteration space tiling is a common strategy used by parallelizing compilers and in performance tuning of parallel codes. We address the problem of determining the tile size that minimizes the total execution time of such a program. We restrict our attention to uniform dependency computations which have a parallelogram shaped two dimensional iteration space, and the target architecture is a linear array (or a ring). Our approach is an extension of the space-time mapping used in systolic synthesis, together with a realistic model of general purpose parallel machines, abstracted by just two parameters, tile period, P t and inter-tile latency, L t . The problem then reduces to a discrete nonlinear optimization problem. We illustrate the method on two examples: the knapsack dynamic programming recurrence (which actually has non-uniform dependencies, but which turn out to be "benign"), and a path planning algorithm due to Bitz and Kung. We show that in both cases the problem formulation i...